VHDL——三态门设计

1.逻辑元件图

三态门都有一个EN控制使能端，来控制门电路的通断

2.VHDL语言

library ieee;
use ieee.std_logic_1164.all;

entity tristate is
    port(din,en : in std_logic;
	      dout : out std_logic);
end tristate;

architecture behave of tristate is
begin
  process(en)
  begin
   if en = '1' then dout <= din;
   else dout <= 'Z';              --high impedance
   end if;
  end process;	
end behave;