三态门的设计

//设计一个三态门电路，可以实现数据的输出和总线“挂起”

module santai_gata(
	input					clk,
	input					rst_n,
	input					data_buf,
	inout				   sda
);

reg flag;
reg [10:0] counter;
//当flag ==1，sda等于待发送的data_buf（此时sda为相当于output型），
//当flag ==0，sda的值变成高阻态（此时sda为相当于input型）
assign sda=(flag)?data_buf:1'bz;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		counter<=0;
	else begin
		if(counter<25)
			counter<=counter+1;
		else
			counter<=0;
	end
	
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		flag<=0;
	else begin
		if(counter==25)
			flag<=~flag;
	end

endmodule

 

`timescale 1ns/1ns
module santai_gata_tb;
	reg					clk;
	reg					rst_n;
	reg					data_buf;
	wire				   sda;

initial begin
	clk=0;
	rst_n=0;
	data_buf=0;
	#200.1;
	rst_n=1;
	
	#1000 data_buf=1;
	#1000 data_buf=0;
	#1000 data_buf=1;
	#1000 data_buf=0;
	#1000 data_buf=1;
end

always #10 clk=~clk;



santai_gata santai_gata(
	.clk(clk),
	.rst_n(rst_n),
	.data_buf(data_buf),
	. sda(sda)
);


endmodule