synplify test.prj 内容

使用Synplify综合工具搭建测试环境，在学习了https://blog.csdn.net/mexican007/article/details/81189100文章后，记录下操作过程。

工具启动命令：synplify_premier -batch test.prj

test.prj内容：

#project files

add_file -verilog -vlog_std sysv "top.v"

#implementation: "rev_1"

impl -add rev_1 -type fpga

#implementation attributes

set_option -vlog_std sysv

set_option -project_relative_includes 1

#par_1 attributes

set_option -job par_1 -add par

#device options

set_option -technology VIRTEX-ULTRASCALEPLUS-FPGAS

set_option -part XCVU19P

set_option -package FSVA3824

set_option -speed_grade -2-e

set_option -part_companion ""

#compilation/mapping options

set_option -use_fsm_explorer 0

set_option -top_module "top"

#hdl_compiler_options

set_option -distributed_compile 0

set_option -scm2hydra 0

set_option -hdl_strict_syntax 0

#mapper_without_write_options

set_option -frequency auto

set_option -srs_instrumentation 1

#mapper_options

set_option -write_verilog 1

set_option -write_structural_verilog 0

set_option -write_vhdl 1

#xilinx_options

set_option -rw_check_on_ram 1

set_option -optimize_ngc 1

#xilinx Virtex2

set_option -run_prop_extract 1

set_option -maxfan 10000

set_option -disable_io_insertion 1

set_option -pipe 1

set_option -update_models_cp 0

set_option -retiming 0

set_option -no_sequential_opt 0

set_option -no_sequential_opt_bram_mapping both

set_option -fix_gated_and_generated_clocks 0

#common_options

set_option -add_out_hierarchy 0

set_option -prepare_readback 0

# Xilinx Virtex UltraScale+ FPGAs

set_option -enable_prepacking 1

set_option -use_vivado 1

#flow_options

set_option -use_unified_compile 0

set_option -use_module_idb 1

#sequential_optimization_options

set_option -symbolic_fsm_compiler 1

#Compiler Options

set_option -compiler_compatible 0

set_option -resource_sharing 1

set_option -multi_file_compilation_unit 1

#Compiler Options

set_option -allow_duplicate_modules 1

set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options

set_option -write_apr_constraint 1

#set result format/file last

project -result_file "rev_1/top.edf"

#design plan options

impl -active "rev_1"

synlog.tcl内容：

history clear

project -load test.prj

set_option -part XCVU19P

project -save test.prj

project -close test.prj

查看rev_1目录下的rpt_top_areasrr和top.vm文件确定Area信息。