STM32中的异常与中断（理论）

目录

目录

目录

一、中断的基本概念

二、异常与中断

（一）概述

（二）异常类型

（三）中断控制

（四）向量表（Vector table）

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一、中断的基本概念

中断的定义以及中断工作方式

        中断，即CPU在正常执行程序的过程中，遇到外部(例如常见的按键防抖 / 内部（定时器中断）) 的紧急事件需要处理，暂时中断（中止）当前程序的执行，而转去位事件服务，待服务完毕，再返回到暂停处继续执行原来的程序。

二、异常与中断

（一）概述

《Cortex M3与M4权威指南》章节4.5 P104

Exceptions are events that cause changes to program flow. When one happens, the processor suspends the current executing task and executes a part of the program called the exception handler. After the execution of the exception handler is completed, the processor then resumes normal program execution. In the ARM architecture, interrupts are one type of exception. Interrupts are usually generated from peripheral or external inputs, and in some cases they can be triggered by software. The exception handlers for interrupts are also referred to as Interrupt Service Routines (ISR)。

Each exception source has an exception number. Exception numbers 1 to 15 as system exceptions, and exceptions 16 and above are for interrupts. The design of the NVIC in the Cortex-M3 and Cortex-M4 processors can support up to 240 interrupt inputs. However, in practice the number of interrupt inputs imple mented in the design is far less, typically in the range of 16 to 100. In this way the silicon size of the design can be reduced, which also reduces power consumption。

 

（二）异常类型

1.系统异常

 《Cortex M3与M4权威指南》章节7.2 P232

        1到15是系统异常，数值越小优先级越高。

2.中断 

（三）中断控制

《Cortex M3与M4权威指南》章节7.3 P235、

After reset, all interrupts are disabled and given a priority-level value of 0. Before using any interrupts, you need to:

• Set up the priority level of the required interrupt (this step is optional)
• Enable the interrupt generation control in the peripheral that triggers the interrupt
• Enable the interrupt in the NVIC

In most typical applications, this is all you need to do. When the interrupt triggers, the corresponding Interrupt Service Routine (ISR) will execute (you might need to clear the interrupt request from the peripheral within the handler). The name of the ISR can be found inside the vector table inside the startup code, which is also provided by the microcontroller vendor. The name of the ISR needs to match the name used in the vector table so that the linker can place the starting address of the ISR into the vector table correctly.

（四）向量表（Vector table）

《Cortex M3与M4权威指南》章节4.5.3 P107

When an exception event takes place and is accepted by the processor core, the corresponding exception handler is executed. To determine the starting address of the exception handler, a vector table mechanism is used. The vector table is an array of word data inside the system memory, each representing the starting address of one exception type。

具体内容可在《Cortex M3与M4权威指南》中有