Innovus

1.指定global route和detail route的金属层上下限

setDesignMode -topRoutingLayer 

              -bottomRoutingLayer

2.N12 工艺pr工具避免P48 layer net拐角的问题

addRoutingHalo -lithoHalo -cell

3.给module 设置padding

setPlaceMode -place_global_module_padding <module name> <factor>

4.将invs DB 打包: 将这个包copy到任意地方都可以启动,命令将lef,lib的源文件打包到包里

saveTestCase

5.更新marco 的形状及pin的位置、layer、形状,但是不能更改pin的数量及名字,

replaceLefMarco

   执行之后相应得会在DB中产生*.updatedMarco的文件,下面是文件格式,路径为绝对路径

<lef file path > <cell name>

6.eco时,由于run time限制,希望只绕特定得net,减少时长

setNanoRouteMode -routeSelectedNetOnly true
selectNet <net name >
ecoRoute -target

7.抓取限定区域内net得面积

set net [dbGet [dbGet -p2 [dbQuery -area "$target_box" -overlap_only -layer] .net.name xxx].box
这个会选中覆盖(或部分覆盖)在指定区域上完整的一根net,如果需要只截取目标区域部分的面积,需要配和
dbShape $target_box AND $net 
得到box,再计算面积

 8. Second power pin route

setNanoRouteMode -routeStripeLayerRange 

setNanoRouteMode -routeSelectedNetOnly 

setPGPinUseSignalRoute <cell name > :<pin name>

globalDetailRoute

#####routePGPinUseSignalRoute -nonDefaultRule 1w2s 

9.editCutWire

当对指定区域的指定层进行切割时,不想切断其他层的net,可以用如下的搭配,可以避免

-selected的限制

set tar_layer [lrange [dbGet head.layer.name ] n m]
foreach bb $tar_layer {
    setLayerPreference $bb -isVisible 0
}
editCutWire -box "" -only_visible_wires

10.attachIObuff

specifyCellPad <BUF4> -left 4 -right 4
attachIoBuff -in <BUF4> \
             -basename xxx_ \
             -status fixed

basename:就是定义插入的buff instname的前缀,如上述例子中插入就是instname 为xxx_开头的buff
suffix:与basename正好相反,如-suffix xxx_,插入就是instname 为xxx_结尾的buff
port:就是以port的名字作为io buffer instname的前缀,如port name是reset,那插入buff的名字
      就是reset_***

### Innovus Mesh Layout and Routing Power Grid Issues Solutions #### Understanding the Problem Context When dealing with mesh layout and routing power grid issues within Innovus, several factors can contribute to complications such as insufficient rows for placing switches or improper configuration of voltage areas. Ensuring that all components are correctly placed and connected is crucial for an efficient design process. #### Configuring Voltage Areas Properly To address potential problems related to inserting power switches failing due to not being covered by any row, it's important first to ensure proper setup of voltage areas. This involves defining primary and secondary (backup) power nets accurately while considering how these networks interact through shifter cells and isolation buffers which should be minimized where possible[^1]. For instance, when configuring multi-voltage domains: - Choose appropriate shifters based on supply requirements. - Place isolation devices strategically to reduce always-on buffer usage. This careful planning helps prevent conflicts during placement stages later in the flow. #### Addressing Row Coverage Issues If encountering errors indicating no available rows for switch insertion, consider revisiting both your defined voltage regions alongside physical constraints like standard cell rows/sites availability[^2]. A practical approach includes checking whether there exists enough space between existing blocks/instances allowing new elements without violating DRC rules; adjusting floorplan parameters accordingly may resolve this issue effectively. Additionally, optimizing site utilization ensures better distribution across different sections reducing congestion points leading towards smoother implementation overall. #### Implementing Global Net Connections Correctly Another critical aspect lies within establishing correct global net connections using commands provided by tools like `globalNetConnect`. For example, connecting ground pins (`VSS`) via type-specific options guarantees stable grounding throughout designs preventing floating nodes from causing unexpected behavior downstream processes[^3]: ```tcl globalNetConnect VSS -type pgpin -pin VSS ``` By adhering closely to recommended practices outlined above along with leveraging built-in features offered within EDA software suites including Innovus itself—such challenges surrounding complex SoC layouts become more manageable ensuring higher quality outputs at faster turnaround times.
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