CDR 论文阅读 1

ALL-DIGITAL CLOCK AND DATA RECOVERY

SYED IRFAN AHMED, 2010， Doctor of Philosophy ，Carleton University

1 研究背景

The contributions from this work are listed as follows:
• An understanding is developed using mathematical analysis and modeling as to
why the oversampling CDR architectures progressively perform better with an
increasing OSR in the presence of random, deterministic and asymmetric jitter.
• A unified mathematical analysis is presented that binds all PD architectures using
OSR as a parameter. A system-level behavioral simulation flow emerges that
incorporates the exact and generalized n-x oversampling (NXO) PD equations
derived in this work to simulate CDR performance in the presence of the given
input jitter.
• An understanding develops of how the oversampling CDR architectures morph all
the way from the BBPD architecture to the linear PD architecture and how the
mathematics seems to have little choice but to behave.
• A novel all-digital Data Recovery (DR) architecture is implemented that establishes the data detection window using phases derived from a multi-phase oscillator. This imparts performance robustness over Process, Voltage and Temperature
(PVT) corners while rendering the DR circuit rate-agile, adaptive and portable.
• Novel simulation methods are introduced to reduce the simulation time for transient jitter tolerance (JTOL) characterization. The idea is to exploit the maximum
slope of the jitter sinusoid as this puts the most stress on the CDR tracking performance.

2 系统架构

Phase Detectors

XOR phase detector

Tri-State phase frequency detector

Hogge 's phase detector

Tri-wave Phase Detector

There are three challenges that need to be resolved when using full rate PDs. The
first issue is that the oscillator running at high speed often provides reduced spectral purity
and tuning range. The second issue is the speed requirement imposed upon the flipflops.
The third issue for a HPD is the systematic skew for zero phase difference as proportional
pulses are wider by the CLK-Q delay of the flipflop. At high bit rates, the ripple owing to
the half cycle delay between the proportional and reference pulses is also untenable as the
ripple on a traditional oscillator can unlock the CDR circuit. A reduction of Kvco can alleviate the ripple by reducing the CP current but CDR bandwidth is reduced as well。

Half-rate linear PD

Alexander PD or Bang-Bang PD or Early-Late PD

THalf-rate BBPD

Multi-phase and multi-bit phase detectors

Reference-less, full-rate CDR architectures

Fully-digital CDR systems ：An all-digital DCO-based CDR architecture

Reduced-rate CDR circuits

DLL-based CDR circuits

Phase-selector CDR circuits

Injection-locked CDR architectur

Burst-Mode gated-oscillator CDR architectures

Variable-interval 3x-oversampling CDR architecture

Jitter tracking CDR architectures

All-digital eye-tracking DR architecture

Blind Oversampling CDR

Jitters

3 模型