SV Code Example On VCS

Preface：

Hello everyone, I’m Chu Shenghui. This is my first attempt at writing a technical blog entirely in English.

In this article, I will walk you through running a System Verilog example using VCS, along with the integration of a Makefile script.

• SV code

  module test;
      int a;
      initial begin
          for(int i = 0;i<8;i++) begin
              a = i;
              $display(a);
          end
      end
  endmodule
  

• examine the code ：vlogan -full64 -sverilog -l comp.log -kdb test.sv

• Compile the code：

  vcs -full64 -sverilog test.sv -l com.log
  

  Upon success, the following files will appear：

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• Simulate

  ./simv -l sim.log
  

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Upon success, the following files will apper，By opening the sim.log, you can also view the results above.
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Create Makefile script:

file.list：fine -name "*.sv" > file.list

all:clean com sim

com:
	vcs -full64 -sverilog -f file.list -l comp.log
sim:
	./simv -l sim.log
clean:
	rm -rf ./csrc *.daidir *.log *.vpd *.vdb simv* *.key *race.out*
	rm -rf AN.DB
	rm -rf novas*
	rm -rf DVEfiles
	rm -rf urgReport

Makefile without using file.list：

FILE=test.sv

all:clean com sim

com:
	vcs -full64 -sverilog  ${FILE} -l comp.log
sim:
	./simv -l sim.log
clean:
	rm -rf ./csrc *.daidir *.log *.vpd *.vdb simv* *.key *race.out*
	rm -rf AN.DB
	rm -rf novas*
	rm -rf DVEfiles
	rm -rf urgReport