一、VGA协议
①VGA协议
VGA(Video Graphics Array)是IBM在1987年随PS/2机⼀起推出的⼀种视频，具有分辨率⾼、显⽰速率快、颜⾊丰富等优点，在彩 ⾊显⽰器领域得到了⼴泛的应⽤。不⽀持热插拔，不⽀持⾳频传输。对于⼀些嵌⼊式VGA显⽰系统，可以在不使⽤VGA显⽰卡和计算机的 情况下，实现VGA图像的显⽰和控制。VGA显⽰器具有成本低、结构简单、应⽤灵活的优点。
②VGA端口结构
原理图
VGA端口是视频输出端口，端口一共包含15个管脚，在通常使用的连接方法里面，15个管脚里面的5个是最重要的，他们包括3个基本红，绿，蓝三条基本色彩线和水平与垂直两条控制线
③扫描方式
VGA显示器扫描方式分为逐行扫描和隔行扫描：逐行扫描是扫描从屏幕左上角一点开始，从左像右逐点扫描，每扫描完一行,电子束回到屏幕的左边下一行的起始位置，在这期间，CRT对电子束进行消隐，每行结束时，用行同步信号进行同步；当扫描完所有的行，形成一帧，用场同步信号进行场同步，并使扫描回到屏幕左上方，同时进行场消隐,开始下一帧。隔行扫描是指电子束扫描时每隔一行扫一线，完成一屏后在返回来扫描剩下的线。
（1）隔行扫描
隔行扫描就是每一 帧被分割为两场，每一场包含了一帧中所有的 奇数扫描行或者偶数扫描行，通常是先扫描奇数行得到第一场，然后扫描偶数行得到第二场。
隔行扫描的条件:
①一帧扫描起始点应上一帧起始点相同，以便保证各帧扫描光栅重叠。一帧的总行数Z必须为整数
②相邻两场扫描光栅必须均匀镶嵌，以获得最高清晰度
一帧的总行数必须为奇数，或任何一场必须包含-个半行
（2）逐行扫描
逐行扫描方式是将每帧的所有画面同时显示，一行紧跟一行的扫描方式称为逐行扫描，电子束在在靶面上或者屏幕上的扫描轨迹称为扫描光栅，逐行扫描电流，行偏转线圈、场偏转线圈共同控制电子束的方向
二、VGA显示字符
代码部分：
module VCG(
OSC_50, //原CLK2_50时钟信号
VGA_CLK, //VGA自时钟
VGA_HS, //行同步信号
VGA_VS, //场同步信号
VGA_BLANK, //复合空白信号控制信号 当BLANK为低电平时模拟视频输出消隐电平，此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC, //符合同步控制信号 行时序和场时序都要产生同步脉冲
VGA_R, //VGA绿色
VGA_B, //VGA蓝色
VGA_G); //VGA绿色
input OSC_50; //外部时钟信号CLK2_50
output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;
output [7:0] VGA_R,VGA_B,VGA_G;
parameter H_FRONT = 16; //行同步前沿信号周期长
parameter H_SYNC = 96; //行同步信号周期长
parameter H_BACK = 48; //行同步后沿信号周期长
parameter H_ACT = 640; //行显示周期长
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK; //行空白信号总周期长
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT; //行总周期长耗时
parameter V_FRONT = 11; //场同步前沿信号周期长
parameter V_SYNC = 2; //场同步信号周期长
parameter V_BACK = 31; //场同步后沿信号周期长
parameter V_ACT = 480; //场显示周期长
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK; //场空白信号总周期长
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT; //场总周期长耗时
reg [10:0] H_Cont; //行周期计数器
reg [10:0] V_Cont; //场周期计数器
wire [7:0] VGA_R; //VGA红色控制线
wire [7:0] VGA_G; //VGA绿色控制线
wire [7:0] VGA_B; //VGA蓝色控制线
reg VGA_HS;
reg VGA_VS;
reg [10:0] X; //当前行第几个像素点
reg [10:0] Y; //当前场第几行
reg CLK_25;
always@(posedge OSC_50)
begin
CLK_25=~CLK_25; //时钟
end
assign VGA_SYNC = 1'b0; //同步信号低电平
assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK)); //当行计数器小于行空白总长或场计数器小于场空白总长时，空白信号低电平
assign VGA_CLK = ~CLK_to_DAC; //VGA时钟等于CLK_25取反
assign CLK_to_DAC = CLK_25;
always@(posedge CLK_to_DAC)
begin
if(H_Cont<H_TOTAL) //如果行计数器小于行总时长
H_Cont<=H_Cont+1'b1; //行计数器+1
else H_Cont<=0; //否则行计数器清零
if(H_Cont==H_FRONT-1) //如果行计数器等于行前沿空白时间-1
VGA_HS<=1'b0; //行同步信号置0
if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1
VGA_HS<=1'b1; //行同步信号置1
if(H_Cont>=H_BLANK) //如果行计数器大于等于行空白总时长
X<=H_Cont-H_BLANK; //X等于行计数器-行空白总时长 （X为当前行第几个像素点）
else X<=0; //否则X为0
end
always@(posedge VGA_HS)
begin
if(V_Cont<V_TOTAL) //如果场计数器小于行总时长
V_Cont<=V_Cont+1'b1; //场计数器+1
else V_Cont<=0; //否则场计数器清零
if(V_Cont==V_FRONT-1) //如果场计数器等于场前沿空白时间-1
VGA_VS<=1'b0; //场同步信号置0
if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1
VGA_VS<=1'b1; //场同步信号置1
if(V_Cont>=V_BLANK) //如果场计数器大于等于场空白总时长
Y<=V_Cont-V_BLANK; //Y等于场计数器-场空白总时长 （Y为当前场第几行）
else Y<=0; //否则Y为0
end
reg valid_yr;
always@(posedge CLK_to_DAC)
if(V_Cont == 10'd32) //场计数器=32时
valid_yr<=1'b1; //行输入激活
else if(V_Cont==10'd512) //场计数器=512 时
valid_yr<=1'b0; //行输入冻结
wire valid_y=valid_yr; //连线
reg valid_r;
always@(posedge CLK_to_DAC)
if((H_Cont == 10'd32)&&valid_y) //行计数器=32时
valid_r<=1'b1; //像素输入激活
else if((H_Cont==10'd512)&&valid_y) //行计数器=512时
valid_r<=1'b0; //像素输入冻结
wire valid = valid_r; //连线
wire[10:0] x_dis; //像素显示控制信号
wire[10:0] y_dis; //行显示控制信号
assign x_dis=X; //连线X
assign y_dis=Y; //连线Y
parameter //点阵字模：每一行char_lineXX是显示的一行，共272列
char_line00=272'h000000000000000000000000000000000000000000000000000000000000000000000000 , //第1行
char_line01=272'h00007C000001E00000000000000000000000000000000000000000000000000000000000, //第2行
char_line02=272'h1FF87C000001E00000000000000000000000000000000000000000000000000000000000, //第3行
char_line03=272'h1FF87C000001E00000000000000000000000000000000000000000000000000000000000, //第4行
char_line04=272'h7FF9FC3C0007E03F0000007FC0FF8007803FC007E03FFF81F800FF007E0003C01F803FC0, //第5行
char_line05=272'h7FF9FC3C0007E03F0000007FC0FF8007C03FE007E03FFF81F800FF007E0003C01F803FC0, //第6行
char_line06=272'h79E7FFFC07FFFFFF000001FFF3FFE07FC0FFF81FFC3FFF87FE03FFC1FF800FC07FE0FFF0, //第7行
char_line07=272'h79E7FFFC07FFFFFF000001FFF3FFE07FC0FFF81FFC3FFF87FE03FFE1FF800FC07FE0FFF0, //第8行
char_line08=272'h79E7FFF007FFFFF0000007E3F3C1F87FC0F07E7E7F3C3F9F9FCFCFE7E7E00FC1F9F8F0FC, //第9行
char_line09=272'h79E7FFF007FFFFF0000007E3F3C1F87FC0F07E7E7F3C3F9F9FCFCFC7E7E00FC1F9F8F0FC, //第10行
char_line0a=272'h7FE7EF00001E78000000078003C1F807C0F01E780F3C3E1E07CF000781E03FC1E078F03C, //第11行
char_line0b=272'h7FE7EF00001E78000000078003C1F807C0F01E780F3C3E1E07CF000781E03FC1E078F03C, //第12行
char_line0c=272'h7FE78F00007E7800000007FF0001F807C0F01E780F00FE1E07CFFC0781E0FFC1E078F03C, //第13行
char_line0d=272'h7FE78F00007E7800000007FF0001F007C0F01E780F00FC1E07CFFC0781E0FFC1E078E03C, //第14行
char_line0e=272'h79FFFFFC01FFFFFC000007FFC03FE007C0F01E780F00F01E07CFFF0781E0F3C1E07800FC, //第15行
char_line0f=272'h79FFFFFC01FFFFFC000007F3C03F8007C0F01E780F00F01E07CFCF0781E0F3C1E07800F0, //第16行
char_line10=272'h79FFFFFC01FFFFFC000007E3F03FE007C0FFFE780F00F01E07CFCFE781E3F3C1E07803F0, //第17行
char_line11=272'h7879EF0001FE7B8000000780F001F807C0FFFE780F03F01E07CF03E781E3C3C1E0780FC0, //第18行
char_line12=272'h7879EF0001FE7FC000000780F001F807C0FFFE780F03F01E07CF03E781E3C3C1E0780FC0, //第19行
char_line13=272'h7FFFEFF0001E7FF000000780F0007807C00F1E780F03C01E07CF03E781E3FFC1E0783F00, //第20行
char_line14=272'h7FFFEFF0001E7FF000000780F0007807C00F1E780F03C01E07CF03E781E3FFC1E0783F00, //第21行
char_line15=272'h7FFFEFFC007E78FF00000780F3C07807C0007E780F03C01E07CF03E781E0FFC1E0783C3C, //第22行
char_line16=272'h7FFFEFFC007E78FF00000780F3C07807C0007E780F03C01E07CF03E781E0FFC1E0783C3C, //第23行
char_line17=272'h79FF8F3F01F8783F000007E0F3C1F807C0FC787E7F03C01F9FCFC3E7E7E003C1F9F8FC3C, //第24行
char_line18=272'h79FF8F3F01F8783F000007E0F3C1F807C0FC787E7F03C01F9F8FC3E7E7E003C1F9F8FC3C, //第25行
char_line19=272'h787E0F0F07E0780FC00001FFF3FFE07FF0FFF81FFC03C007FE03FFE1FF803FF07FE0FFFC, //第26行
char_line1a=272'h787E0F0F07E0780FC00001FFF3FFE07FF0FFF01FF803C007FE03FFC1FF803FF07FE0FFFC, //第27行
char_line1b=272'h79F87F0F0787F803C000007FC0FF807FF03FE007E003C001F800FF007E003FF01F80FFFC, //第28行
char_line1c=272'h79F87F0F0707F803C000003FC0FF007FE03FC007E003C001F800FF007E003FF01F80FFFC, //第29行
char_line1d=272'h79E07F000007F80000000000000000000000000000000000000000000000000000000000, //第30行
char_line1e=272'h79C03E000003F80000000000000000000000000000000000000000000000000000000000, //第31行
char_line1f=272'h780000000001E00000000000000000000000000000000000000000000000000000000000; //第32行
reg[8:0] char_bit;
always@(posedge CLK_to_DAC)
if(X==10'd144)char_bit<=9'd272; //当显示到144像素时准备开始输出图像数据
else if(X>10'd144&&X<10'd416) //左边距屏幕144像素到416像素时 416=144+272（图像宽度）
char_bit<=char_bit-1'b1; //倒着输出图像信息
reg[29:0] vga_rgb; //定义颜色缓存
always@(posedge CLK_to_DAC)
if(X>10'd144&&X<10'd416) //X控制图像的横向显示边界：左边距屏幕左边144像素 右边界距屏幕左边界416像素
begin case(Y) //Y控制图像的纵向显示边界：从距离屏幕顶部160像素开始显示第一行数据
10'd160:
if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000; //如果该行有数据 则颜色为红色
else vga_rgb<=30'b0000000000_0000000000_0000000000; //否则为黑色
10'd162:
if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd163:
if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd164:
if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd165:
if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd166:
if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd167:
if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd168:
if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd169:
if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd170:
if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd171:
if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd172:
if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd173:
if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd174:
if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd175:
if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd176:
if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd177:
if(char_line10[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd178:
if(char_line11[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd179:
if(char_line12[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd180:
if(char_line13[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd181:
if(char_line14[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd182:
if(char_line15[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd183:
if(char_line16[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd184:
if(char_line17[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd185:
if(char_line18[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd186:
if(char_line19[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd187:
if(char_line1a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd188:
if(char_line1b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd189:
if(char_line1c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd190:
if(char_line1d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd191:
if(char_line1e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
10'd192:
if(char_line1f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;
else vga_rgb<=30'b0000000000_0000000000_0000000000;
default:vga_rgb<=30'h0000000000; //默认颜色黑色
endcase
end
else vga_rgb<=30'h000000000; //否则黑色
assign VGA_R=vga_rgb[23:16];
assign VGA_G=vga_rgb[15:8];
assign VGA_B=vga_rgb[7:0];
endmodule
三、VGA显示彩带
代码
顶层文件
module vga_top(
input wire clk,
input wire rst_n,
output wire hsync,
output wire vsync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
output wire vga_clk,
output wire vga_sync ,
output wire vga_blk
);
wire [23:0] data_dis;
wire [10:0] h_addr;
wire [10:0] v_addr;
data_gen data_gen_inst(
.clk (clk),
.rst_n (rst_n),
.h_addr (h_addr),
.v_addr (v_addr),
.data_dis (data_dis)
);
vga_ctrl vga_ctrl_inst(
.clk (clk),
.rst_n (rst_n),
.data_dis (data_dis ),
.h_addr (h_addr),//数据有效显示区域行地址
.v_addr (v_addr),//数据有效显示区域场地址
.hsync (hsync),
.vsync (vsync),
.vga_r (vga_r),
.vga_g (vga_g),
.vga_b (vga_b),
.vga_clk (vga_clk),
.vga_sync (vga_sync ),
.vga_blk (vga_blk)
);
endmodule
data_gen文件
module data_gen(
input wire clk,
input wire rst_n,
input wire [10:0] h_addr,
input wire [10:0] v_addr,
output reg [23:0] data_dis
);
parameter BLACK = 24'h000000,
RED = 24'hFF0000,
GREEN = 24'h00FF00,
BLUE = 24'h0000FF,
YELLOW = 24'hFFFF00,
SKY_BULE = 24'h00FFFF,
PURPLE = 24'hFF00FF,
GRAY = 24'hC0C0C0,
WHITE = 24'hFFFFFF;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_dis <= WHITE;
end
else begin
case(h_addr)
0 : data_dis <= BLACK ;
80 : data_dis <= RED ;
160: data_dis <= GREEN ;
240: data_dis <= BLUE ;
320: data_dis <= YELLOW ;
400: data_dis <= SKY_BULE ;
480: data_dis <= PURPLE ;
560: data_dis <= GRAY;
default: data_dis <= data_dis;
endcase
end
end
endmodule
vga_ctrl文件
`define vga_640_480
`include "vga_param.v"
module vga_ctrl(
input clk ,//时钟信号 //25.2MHZ
input rst_n ,//复位信号
input [23:0] data_dis ,
output reg [10:0] h_addr ,//数据有效显示区域行地址
output reg [10:0] v_addr ,//数据有效显示区域场地址
output reg vsync ,
output reg hsync ,
output reg [7 :0] vga_r ,
output reg [7 :0] vga_b ,
output reg [7 :0] vga_g ,
output wire vga_blk ,
output wire vga_sync ,
output reg vga_clk //25.2MHZ
);
//参数定义
parameter H_SYNC_START = 1,
H_SYNC_STOP = `H_Sync_Time ,
H_DATA_START = `H_Sync_Time + `H_Back_Porch + `H_Left_Border,
H_DATA_STOP = `H_Sync_Time + `H_Back_Porch + `H_Left_Border + `H_Data_Time,
V_SYNC_START = 1,
V_SYNC_STOP = `V_Sync_Time,
V_DATA_START = `V_Sync_Time + `V_Back_Porch + `V_Top_Border,
V_DATA_STOP = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;
//信号定义
reg [11:0] cnt_h_addr ;//行地址计数器
wire add_h_addr ;
wire end_h_addr ;
reg [11:0] cnt_v_addr ;//长地址计数器
wire add_v_addr ;
wire end_v_addr ;
assign vga_sync = 1'b0;
assign vga_blk = ~((cnt_h_addr<`H_Front_Porch + `H_Sync_Time + `H_Back_Porch)||(cnt_v_addr<`V_Front_Porch + `V_Sync_Time + `V_Back_Porch));
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_h_addr <= 12'd0;
end
else if(add_h_addr)begin
if(end_h_addr)begin
cnt_h_addr <= 12'd0;
end
else begin
cnt_h_addr <= cnt_h_addr + 12'd1;
end
end
else begin
cnt_h_addr <= 12'd0;
end
end
assign add_h_addr = 1'b1;
assign end_h_addr = add_h_addr && cnt_h_addr == `H_Total_Time - 1;
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_v_addr <= 12'd0;
end
else if(add_v_addr)begin
if(end_v_addr)begin
cnt_v_addr <= 12'd0;
end
else begin
cnt_v_addr <= cnt_v_addr + 12'd1;
end
end
else begin
cnt_v_addr <= cnt_v_addr;
end
end
assign add_v_addr = end_h_addr;
assign end_v_addr = add_v_addr && cnt_v_addr == `V_Total_Time - 1;
//行场同步信号
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
hsync <= 1'b1;
end
else if(cnt_h_addr == H_SYNC_START - 1)begin
hsync <= 1'b0;
end
else if(cnt_h_addr == H_SYNC_STOP - 1)begin
hsync <= 1'b1;
end
else begin
hsync <= hsync;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vsync <= 1'b1;
end
else if(cnt_v_addr == V_SYNC_START - 1)begin
vsync <= 1'b0;
end
else if(cnt_v_addr == V_SYNC_STOP - 1)begin
vsync <= 1'b1;
end
else begin
vsync <= vsync;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
vga_clk =0;
end
else begin
vga_clk = ~vga_clk;
end
end
//数据有效显示区域定义
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
h_addr <= 11'd0;
end
else if((cnt_h_addr >= H_DATA_START - 1) &&( cnt_h_addr <= H_DATA_STOP - 1))begin
h_addr <= cnt_h_addr - H_DATA_START - 1;
end
else begin
h_addr <= 11'd0;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
v_addr <= 11'd0;
end
else if((cnt_v_addr >= V_DATA_START - 1) && (cnt_v_addr <= V_DATA_STOP - 1))begin
v_addr <= cnt_v_addr - V_DATA_START -1;
end
else begin
v_addr <= 11'd0;
end
end
//显示数据
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vga_r <= 8'b0;
vga_g <= 8'b0;
vga_b <= 8'b0;
end
else if((cnt_h_addr >= H_DATA_START - 1) &&( cnt_h_addr <= H_DATA_STOP - 1)
&& (cnt_v_addr >= V_DATA_START - 1) && (cnt_v_addr <= V_DATA_STOP - 1))begin
vga_r <= data_dis[23:16];
vga_g <= data_dis[15: 8];
vga_b <= data_dis[7 : 0];
end
else begin
vga_r <= 8'b0;
vga_g <= 8'b0;
vga_b <= 8'b0;
end
end
endmodule
vga_640_480文件
`define vga_640_480
//`define vga_480_272
//`define vga_800_480
//`define vga_800_600
//`define vga_1024_600
//`define vga_1024_768
//`define vga_1280_720
//`define vga_1920_1080
`ifdef vga_640_480
`define H_Right_Border 8
`define H_Front_Porch 8
`define H_Sync_Time 96
`define H_Back_Porch 40
`define H_Left_Border 8
`define H_Data_Time 640
`define H_Toal_Time 800
`define V_Bottom_Border 8
`define V_Front_Porch 2
`define V_Sync_Time 2
`define V_Back_Porch 25
`define V_Top_Border 8
`define V_Data_Time 480
`define V_Total_Time 525
`elsif vga_480_272
`define H_Right_Border 0
`define H_Front_Porch 2
`define H_Sync_Time 41
`define H_Back_Porch 2
`define H_Left_Border 0
`define H_Data_Time 480
`define H_Toal_Time 525
`define V_Bottom_Border 0
`define V_Front_Porch 2
`define V_Sync_Time 10
`define V_Back_Porch 2
`define V_Top_Border 0
`define V_Data_Time 272
`define V_Total_Time 286
`elsif vga_800_480
`define H_Right_Border 0
`define H_Front_Porch 40
`define H_Sync_Time 128
`define H_Back_Porch 88
`define H_Left_Border 0
`define H_Data_Time 800
`define H_Toal_Time 1056
`define V_Bottom_Border 8
`define V_Front_Porch 2
`define V_Sync_Time 2
`define V_Back_Porch 25
`define V_Top_Border 8
`define V_Data_Time 480
`define V_Total_Time 525
`elsif vga_800_600
`define H_Right_Border 0
`define H_Front_Porch 40
`define H_Sync_Time 128
`define H_Back_Porch 88
`define H_Left_Border 0
`define H_Data_Time 800
`define H_Toal_Time 1056
`define V_Bottom_Border 0
`define V_Front_Porch 1
`define V_Sync_Time 4
`define V_Back_Porch 23
`define V_Top_Border 0
`define V_Data_Time 600
`define V_Total_Time 628
`elsif vga_1024_600
`define H_Right_Border 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Toal_Time 1344
`define V_Bottom_Border 0
`define V_Front_Porch 1
`define V_Sync_Time 4
`define V_Back_Porch 23
`define V_Top_Border 0
`define V_Data_Time 600
`define V_Total_Time 628
`elsif vga_1024_768
`define H_Right_Border 0
`define H_Front_Porch 24
`define H_Sync_Time 136
`define H_Back_Porch 160
`define H_Left_Border 0
`define H_Data_Time 1024
`define H_Toal_Time 1344
`define V_Bottom_Border 0
`define V_Front_Porch 3
`define V_Sync_Time 6
`define V_Back_Porch 29
`define V_Top_Border 0
`define V_Data_Time 768
`define V_Total_Time 806
`elsif vga_1280_720
`define H_Right_Border 0
`define H_Front_Porch 110
`define H_Sync_Time 40
`define H_Back_Porch 220
`define H_Left_Border 0
`define H_Data_Time 1280
`define H_Toal_Time 1650
`define V_Bottom_Border 0
`define V_Front_Porch 5
`define V_Sync_Time 5
`define V_Back_Porch 20
`define V_Top_Border 0
`define V_Data_Time 720
`define V_Total_Time 750
`elsif vga_1920_1080
`define H_Right_Border 0
`define H_Front_porch 88
`define H_Sync_Time 44
`define H_Back_Porch 148
`define H_Left_Border 0
`define H_Data_Time 1920
`define H_Toal_Time 2200
`define V_Bottom_Border 0
`define V_Front_Porch 4
`define V_Sync_Time 5
`define V_Back_Porch 36
`define V_Top_Border 0
`define V_Data_Time 1080
`define V_Total_Time 1125
`endif
结果图
四、VGA显示图片
代码部分
vga_top文件
module vga_top(
input wire clk,
input wire rst_n,
output wire hsync,
output wire vsync,
output wire [7:0] vga_r,
output wire [7:0] vga_g,
output wire [7:0] vga_b,
output wire vga_blk,
output wire vga_clk
);
wire [23:0] data_dis;
wire [10:0] h_addr;
wire [10:0] v_addr;
data_gen data_gen(
.vga_clk (vga_clk),
.rst_n (rst_n),
.h_addr (h_addr),
.v_addr (v_addr),
.data_dis (data_dis)
);
vga_ctrl vga_ctrl(
.clk (clk),
.rst_n (rst_n),
.data_dis (data_dis),
.h_addr (h_addr),//数据有效显示区域行地址
.v_addr (v_addr),//数据有效显示区域场地址
.hsync (hsync),
.vsync (vsync),
.vga_r (vga_r),
.vga_g (vga_g),
.vga_b (vga_b),
.vga_blk (vga_blk),
.vga_clk (vga_clk)
);
endmodule
vga_ctrl文件
`define vga_640_480
`include "vga_param.v"
module vga_ctrl(
input wire clk ,
input wire rst_n ,
input wire [23:0] data_dis ,
output reg [10:0] h_addr ,//数据有效显示区域行地址
output reg [10:0] v_addr ,//数据有效显示区域场地址
output reg hsync ,
output reg vsync ,
output reg [7:0] vga_r ,
output reg [7:0] vga_g ,
output reg [7:0] vga_b ,
output reg vga_blk ,
output wire vga_clk
);
parameter H_SYNC_STA = 1,
H_SYNC_STO = `H_Sync_Time,
H_DATA_STA = `H_Sync_Time + `H_Back_Porch + `H_Left_Border,
H_DATA_STO = `H_Sync_Time + `H_Back_Porch + `H_Left_Border + `H_Data_Time;
parameter V_SYNC_STA = 1,
V_SYNC_STO = `V_Sync_Time,
V_DATA_STA = `V_Sync_Time + `V_Back_Porch + `V_Top_Border,
V_DATA_STO = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;
reg [11:0] cnt_h_addr;//行地址计数器
wire add_h_addr ;
wire end_h_addr ;
reg [11:0] cnt_v_addr;//列地址计数器
wire add_v_addr ;
wire end_v_addr ;
wire clk_25 ;
clk_25 clk_25_inst (
.areset ( ~rst_n ),
.inclk0 ( clk ),
.c0 ( clk_25 )
);
assign vga_clk = ~clk_25;
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_h_addr <= 12'd0;
end
else if(add_h_addr)begin
if(end_h_addr)begin
cnt_h_addr <= 12'd0;
end
else begin
cnt_h_addr <= cnt_h_addr + 12'd1;
end
end
else begin
cnt_h_addr <= 12'd0;
end
end
assign add_h_addr = 1'b1;
assign end_h_addr = add_h_addr && cnt_h_addr >= `H_Total_Time - 1;
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
cnt_v_addr <= 12'd0;
end
else if(add_v_addr)begin
if(end_v_addr)begin
cnt_v_addr <= 12'd0;
end
else begin
cnt_v_addr <= cnt_v_addr + 12'd1;
end
end
else begin
cnt_v_addr <= cnt_v_addr;
end
end
assign add_v_addr = end_h_addr;
assign end_v_addr = add_v_addr && cnt_v_addr >= `V_Total_Time - 1;
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
hsync <= 1'b1;
end
else if(cnt_h_addr == H_SYNC_STA- 1)begin
hsync <= 1'b0;
end
else if(cnt_h_addr == H_SYNC_STO - 1)begin
hsync <= 1'b1;
end
else begin
hsync <= hsync;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vsync <= 1'b1;
end
else if(cnt_v_addr == V_SYNC_STA - 1)begin
vsync <= 1'b0;
end
else if(cnt_v_addr == V_SYNC_STO - 1)begin
vsync <= 1'b1;
end
else begin
vsync <= vsync;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
h_addr <= 11'd0;
end
else if((cnt_h_addr >= H_DATA_STA - 1) && (cnt_h_addr <= H_DATA_STO -1) )begin
h_addr <= cnt_h_addr - H_DATA_STA + 1;
end
else begin
h_addr <= 11'd0;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
v_addr <= 11'd0;
end
else if((cnt_v_addr >= V_DATA_STA - 1) && (cnt_v_addr <= V_DATA_STO -1) )begin
v_addr <= cnt_v_addr - V_DATA_STA + 1;
end
else begin
v_addr <= 11'd0;
end
end
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n)begin
vga_r <= 8'b0;
vga_g <= 8'b0;
vga_b <= 8'b0;
vga_blk <= 1'b0;
end
else if((cnt_h_addr >= H_DATA_STA - 1) && (cnt_h_addr <= H_DATA_STO -1) &&
(cnt_v_addr >= V_DATA_STA - 1) && (cnt_v_addr <= V_DATA_STO -1) )begin
vga_r <= data_dis[23:16];
vga_g <= data_dis[15:8];
vga_b <= data_dis[7:0];
vga_blk <= 1'b1;
end
else begin
vga_r <= 8'b0;
vga_g <= 8'b0;
vga_b <= 8'b0;
vga_blk <= 1'b0;
end
end
endmodule
data_gen文件
module data_gen(
input wire vga_clk,
input wire rst_n,
input wire [10:0] h_addr,
input wire [10:0] v_addr,
output reg [23:0] data_dis
);
parameter BLACK = 24'h000000,
RED = 24'hFF0000,
GREEN = 24'h00FF00,
BLUE = 24'h0000FF,
YELLOW = 24'hFFFF00,
SKY_BULE = 24'h00FFFF,
PURPLE = 24'hFF00FF,
GRAY = 24'hC0C0C0,
WHITE = 24'hFFFFFF;
wire flag_begin_h ; // 图片显示行
wire flag_begin_v ; // 图片显示列
parameter height = 78; // 图片高度
parameter width = 128; // 图片宽度
reg [ 13:0 ] rom_address ; // ROM地址
wire [ 23:0 ] rom_data ;
//ROM地址计数器
always@(posedge vga_clk or negedge rst_n)begin
if(!rst_n )begin
data_dis = WHITE;
end
else if(flag_enable_out2)begin
data_dis = rom_data;
end
else begin
data_dis = WHITE;
end
end
always @( posedge vga_clk or negedge rst_n ) begin
if ( !rst_n ) begin
rom_address <= 0;
end
else if ( rom_address == 9983 ) begin //计数满清零
rom_address <= 0;
end
else if ( flag_enable_out2 ) begin //在有效区域内+1
rom_address <= rom_address + 1;
end
else begin //无效区域保持
rom_address <= rom_address;
end
end
assign flag_begin_h = h_addr > ( ( 640 - width ) / 2 ) && h_addr < ( ( 640 - width ) / 2 ) + width + 1;
assign flag_begin_v = v_addr > ( ( 480 - height )/2 ) && v_addr <( ( 480 - height )/2 ) + height + 1;
assign flag_enable_out2 = flag_begin_h && flag_begin_v;
rom rom_inst (
.address ( rom_address ),
.clock ( vga_clk ),
.q ( rom_data )
);
endmodule
结果图
五、参考文献
https://blog.csdn.net/junseven164/article/details/125165822?spm=1001.2014.3001.5502
https://www.cnblogs.com/xianyufpga/p/11128817.html
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