合工大计算机组成实验2-4

实验二

仿真结果如下:

`timescale 1ps / 1ps           // timescale前的符号是`
module flash_led_top_tb;
reg clk,rst,sw0;  
//定义仿真时输入引脚,由于是仿真，所以定义为reg类型。
 	 	wire [15:0] led;        //定义仿真时输出引脚，为wire类型。
 	  	initial begin          //在initial语句中，给输入信号进行赋值
 	 		clk = 1'b0;    
 	 		rst = 1'b1;
 	 		sw0 = 1'b0;
 	 		#10 rst = 1'b0;
 	 		#10 rst = 1'b1;
 	 		#1000000000				
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000
 	 		#1000000000              //6ms后改变位移方向
 	 		sw0 = 1'b1;
 	 	end
 	 	always #5 clk <= ~clk;         //在always过程语句中，对clk取反
 	 	flash_led_top flash_led_top(
 	 		.clk( clk ),
 	 		.rst_n( rst ),
 	 		.sw0( sw0 ),
 	 		.led( led )
 	 	);              //对顶层电路进行元件例化，固定例化后引脚名字。
endmodule

实验三

编码器的编写:

仿真结果如下:

激励文件代码如下

`timescale 1ns / 1ps

module encoder8_3_tb;
reg [7:0] d;
wire[2:0] Q;
initial begin
d = 8'b01111111;
#10 d = 8'b10111111;
#10 d = 8'b11011111;
#10 d = 8'b11101111;
#10 d = 8'b11110111;
#10 d = 8'b11111011;
#10 d = 8'b11111101;
#10 d = 8'b11111110; // 此时输出应为高阻态
end
encoder8_3 encoder8_3(
.d(d),.Q(Q)
);
endmodule

译码器的编写

仿真结果如下:

代码如下

`timescale 1ns / 1ps

module encoder8_3_tb;
reg[3:0] DB;
wire[6:0] SEG;
initial begin
    DB = 4'd2;
    #10 DB=4'd1;
    #10 DB=4'd8;
    #10 DB=4'd1;
    #10 DB=4'd8;
    #10 DB=4'd3;   
end;
encoder8_3 encoder8_3(
        .DB(DB), .SEG(SEG)      
);
endmodule

比较器的编写:

仿真结果如下
![在这里插入图片描述](https://img-blog.csdnimg.cn/3e19f612d88c4a67a8f75695d3c4e240.png

激励文件代码如下:

`timescale 1ns / 1ps

module comp_tb;
reg CLK,RST;
reg[2:0] A,B;

wire AGTB,ALTB,AEQB;

initial begin
    CLK = 1'b0;
    RST = 1'b0;
    #10 A <=8'h81;	//学号后四位为8183
    B <= 8'h83;
    #10;
end
always #5
    CLK = ~CLK;
always #10 begin
    A=A+1'b1;
    B=B+1'b1;
    if (A == 3'b111) A = 3'b000;
    if (B == 3'b111) A = 3'b000;
end

comp uut(
.CLK(CLK), .RST(RST), .A(A), .B(B),
.AGTB(AGTB), .ALTB(ALTB), .AEQB(AEQB)
);

endmodule

全加器的编写

仿真结果如下

激励文件代码如下

`timescale 1ns / 1ps
module full_adder_tb;
reg [3:0] a,b;
reg cin;
wire [3:0] sum;
wire cout;
initial begin//学号后四位为8183
a = 4'b0001;//赋值为1
b = 4'b0011;//赋值为3
cin = 1'b0;
end
always #10 begin
a = a+1;
b = b+1;
cin = ~cin;
end
ful_adder uut(
.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout)
);
endmodule

实验四

基本D触发器

仿真结果如下:

代码如下

`timescale 1ns / 1ps
module trigger_d_tb;
reg d,clk;
wire Q;
wire Qd;

initial begin
    d = 1'b0;
    clk = 1'b0;
end

always #5 begin
    clk = ~clk;
end

always #83 begin
    d = d^clk;
end

D uut(
.d(d),.clk(clk),.Q(Q),.Qd(Qd)
);
endmodule

同步复位D触发器

仿真结果如下:

激励文件代码如下

module sync_rddf(clk , reset, d, Q, Qb);
input  clk,reset,d;
output Q,Qb;
reg  Q,Qb;
always@(posedge  clk)
 begin
if(!reset)
begin
Q<= 0;
Qb<=1;
end
else
begin
Q <= d;
Qb<= ~d;
end
end
endmodule

异步复位D触发器

仿真结果如下

激励文件代码如下

`timescale 1ns / 1ps
module async_rddf_tb;
reg clk,reset,d;
wire Q,Qb;
initial begin
clk = 1'b0;
reset = 1'b0;
d = 1'b0;
end
always #10 begin
clk = ~clk;
end
always #83 begin
reset = ~reset;
d = d^reset;
end

async_rddf uut(
.clk(clk),.reset(reset),.d(d),.Q(Q),.Qb(Qb)
);
endmodule

同步/异步触发器

仿真结果如下

激励文件源码如下

`timescale 1ns/1ps
module sync_rsddf_tb;
reg clk,reset,set;
reg d;
wire Q,Qb;
initial begin
clk = 1'b0;
reset = 1'b0;
set = 1'b0;
#10 d = 1'b1;
end
always #5 begin
clk = ~clk;
end
always #89 begin
reset = ~reset;
set = ~set;
end
always #183
d = reset^d;
sync_rsddf uut(
.clk(clk),.reset(reset),.set(set),.d(d),.Q(Q),.Qb(Qb)
);
endmodule

加法计数器

仿真结果如下

激励文件代码如下

`timescale 1ns/1ps
module addcounter_tb;
reg clk;
wire [3:0] Q;
initial begin
clk = 1'b0;
end
always #5 begin
clk = ~clk;
end
addcounter uut(
.clk(clk),.Q(Q)
);
endmodule

减法计数器

仿真结果如下图

上图与学号关联实现了模13加法计算。
激励文件源码如下

module addcounter(clk,Q);
input clk ;
output[3 :0] Q;
reg[3 :0] Q;
initial
begin
Q = 4'hf;
end
always@(posedge clk)
begin
Q=Q-1 ;
if (Q==4'b1011) begin
Q = 4'b1111;
end
end
endmodule