作业代码集

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已于 2023-11-27 23:08:10 修改

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文章标签： fpga开发

于 2023-11-27 23:01:45 首次发布

本文链接：https://blog.csdn.net/m0_64944188/article/details/134656772

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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fenpin IS
PORT(				  CLK_50MHz : IN STD_LOGIC;
	CLK_1Hz, CLK_250Hz, CLK_500Hz, CLK_1000Hz : OUT STD_LOGIC);
END;

ARCHITECTURE BHV OF fenpin IS
SIGNAL Q1 : INTEGER RANGE 0 TO 49999999;--1hz 1s
SIGNAL Q2 : INTEGER RANGE 0 TO 199999;  --250hz
SIGNAL Q3 : INTEGER RANGE 0 TO 99999; --50hz 20ms
SIGNAL Q4 : INTEGER RANGE 0 TO 49999; --1000hz 
BEGIN
	PROCESS(CLK_50MHz) BEGIN
		IF CLK_50MHz'EVENT AND CLK_50MHz = '1' THEN
		   -- 1Hz
			IF Q1 < 25000000		THEN CLK_1Hz <= '0'; Q1 <= Q1 + 1; --50%的占空比
			ELSIF Q1 < 49999999		THEN CLK_1Hz <= '1'; Q1 <= Q1 + 1;
			ELSE Q1 <= 0;
			END IF;
			-- 250Hz
			IF Q2 < 100000		THEN CLK_250Hz <= '0'; Q2 <= Q2 + 1;
			ELSIF Q2 < 199999		THEN CLK_250Hz <= '1'; Q2 <= Q2 + 1; 
			ELSE Q2 <= 0;
			END IF;
			-- 500Hz 
			IF Q3 < 50000	THEN CLK_500Hz <= '0'; Q3 <= Q3 + 1;
			ELSIF Q3 < 99999	THEN CLK_500Hz <= '1'; Q3 <= Q3 + 1; 
			ELSE Q3 <= 0;
			END IF;
			--1000Hz
			IF Q4 < 25000		THEN CLK_1000Hz <= '0'; Q4 <= Q4 + 1; --50%的占空比
			ELSIF Q4 < 49999		THEN CLK_1000Hz <= '1'; Q4 <= Q4 + 1;
			ELSE Q4 <= 0;
			END IF;
		END IF;
	END PROCESS;
END;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY shizhongjishuqi IS
PORT(clk_to_hour, reset : IN STD_LOGIC;
						 DATOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END shizhongjishuqi;

ARCHITECTURE BHV OF shizhongjishuqi IS
SIGNAL COUNT_SHI, COUNT_GE : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 
	PROCESS(clk_to_hour, reset)  	BEGIN
		IF reset = '0'		THEN COUNT_SHI <= "0000"; COUNT_GE <= "0000"; -- 有复位信号，则清除计数。
		ELSIF clk_to_hour'EVENT AND clk_to_hour = '1'    THEN  --开始计数
			IF COUNT_SHI = "0010" AND COUNT_GE = "0011"		THEN COUNT_SHI <= "0000"; COUNT_GE <= "0000";  -- 24进制溢出清零
			ELSIF COUNT_GE < "1001"		THEN COUNT_GE <= COUNT_GE + 1;
			ELSE COUNT_GE <= "0000"; COUNT_SHI <= COUNT_SHI + 1;
			END IF;
		END IF;
	DATOUT <= COUNT_SHI & COUNT_GE;  -- 数据输出
	END PROCESS;
END BHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fenzhongjishuqi IS
PORT(clk_to_minute, reset, set_hour : IN STD_LOGIC;
                                 CO : OUT STD_LOGIC; --分向时的进位
		                     DATOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END fenzhongjishuqi;

ARCHITECTURE BHV OF fenzhongjishuqi IS
SIGNAL COUNT_SHI, COUNT_GE : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNT_EN : STD_LOGIC;
BEGIN 
   CO <=  set_hour OR COUNT_EN;
	PROCESS(clk_to_minute, set_hour, reset)  	BEGIN   
		IF reset = '0'		THEN COUNT_SHI <= "0000"; COUNT_GE <= "0000"; -- 有复位信号，则清除计数
		ELSIF clk_to_minute'EVENT AND clk_to_minute = '1'   THEN	     --开始计数
			IF COUNT_SHI = "0101" AND COUNT_GE  = "1001"   THEN     --0-59
				COUNT_SHI <= "0000"; COUNT_GE <= "0000";  COUNT_EN <= '1';  -- 计数进位（信号量不是立即赋值，需等下一个时钟信号到来。）
			ELSIF COUNT_GE < "1001" 	THEN COUNT_GE <= COUNT_GE + 1; COUNT_EN <= '0'; 
			ELSE COUNT_GE <= "0000";  -- 计数溢出则清零，并产生进位
				IF COUNT_SHI < "1010" 	THEN COUNT_SHI <= COUNT_SHI + 1;  
				ELSE COUNT_SHI <= "0000";  
				END IF;
			END IF;
		END IF;
	END PROCESS;
	DATOUT <= COUNT_SHI & COUNT_GE;  -- 数据输出
END BHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY miaozhongjishuqi IS
PORT(clk_to_second, reset, set_min : IN STD_LOGIC;
                                CO : OUT STD_LOGIC;
		                    DATOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END miaozhongjishuqi;

ARCHITECTURE BHV OF miaozhongjishuqi IS
SIGNAL COUNT_SHI, COUNT_GE : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNT_EN : STD_LOGIC;
BEGIN 
   CO <= set_min OR COUNT_EN;
	PROCESS(clk_to_second, reset, set_min)  	BEGIN
   IF reset = '0'		THEN COUNT_SHI <= "0000"; COUNT_GE <= "0000"; -- 有复位信号，则清除计数
	ELSIF clk_to_second'EVENT AND clk_to_second = '1'   THEN	 
		IF COUNT_SHI = "0101" AND COUNT_GE  = "1001"   THEN 
			COUNT_SHI <= "0000"; COUNT_GE <= "0000";  COUNT_EN <= '1';  -- 计数进位（信号量不是立即赋值，需等下一个时钟信号到来。）
		ELSIF COUNT_GE < "1001" 	THEN COUNT_GE <= COUNT_GE + 1;  COUNT_EN <= '0';
		ELSE COUNT_GE <= "0000";  
			IF COUNT_SHI < "1010" 	THEN COUNT_SHI <= COUNT_SHI + 1;  
			ELSE COUNT_SHI <= "0000";  
			END IF;
		END IF;
	END IF;
	DATOUT <= COUNT_SHI & COUNT_GE;  -- 数据输出
	END PROCESS;
END BHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY xiaodou IS
PORT(CLK, KEY_IN : IN STD_LOGIC;  
         KEY_OUT : OUT STD_LOGIC);
END xiaodou;

ARCHITECTURE BHV OF xiaodou IS
BEGIN
PROCESS(CLK, KEY_IN)
VARIABLE COUNT : INTEGER RANGE 0 TO 10;
BEGIN
	IF CLK'EVENT AND CLK = '1' THEN
		IF KEY_IN = '0' THEN
			IF COUNT < 10	 THEN COUNT := COUNT + 1;
			ELSE COUNT := COUNT;  -- 赋予变量的值是即刻生效的，在此后的代码中，此变量将使用新的变量值。
			END IF;
			IF COUNT = 9	THEN KEY_OUT <= '1';	
			ELSE KEY_OUT <= '0';	
			END IF;
		ELSE COUNT := 0;
		END IF;
	END IF;
END PROCESS;
END BHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY xianshi IS
PORT(            SCAN_CLK : IN STD_LOGIC;  -- 扫描时钟输入 
     HOUR, MINUTE, SECOND : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 时间数据输入
                      SEL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);  -- 位选信号输出
                      SEG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));  -- 段选信号输出
END xianshi;

ARCHITECTURE BHV OF xianshi IS
SIGNAL SCAN_COUNT : STD_LOGIC_VECTOR(2 DOWNTO 0);  -- 扫描计数 
SIGNAL DAT : STD_LOGIC_VECTOR(3 DOWNTO 0);  
BEGIN 	
   -- 位选扫描进程 
	SCAN : PROCESS(SCAN_CLK) BEGIN
		IF SCAN_CLK'EVENT AND SCAN_CLK = '1'   THEN 
			IF(SCAN_COUNT > "101")	THEN SCAN_COUNT <= "000";
			ELSE SCAN_COUNT <= SCAN_COUNT + 1;
			END IF;
		END IF;
		CASE SCAN_COUNT IS
			WHEN "000" => DAT <= SECOND(3 DOWNTO 0);
			WHEN "001" => DAT <= SECOND(7 DOWNTO 4);
			WHEN "010" => DAT <= MINUTE(3 DOWNTO 0);
			WHEN "011" => DAT <= MINUTE(7 DOWNTO 4);
			WHEN "100" => DAT <= HOUR(3 DOWNTO 0);
			WHEN "101" => DAT <= HOUR(7 DOWNTO 4);
			WHEN  OTHERS => NULL;
		END CASE;
	END PROCESS SCAN;
	-- 译码显示进程 共数码管编码 段选
	DECODE :	PROCESS(SCAN_COUNT) BEGIN
		CASE DAT IS
			WHEN "0000" => SEG<="11000000"; 
			WHEN "0001" => SEG<="11111001"; 
			WHEN "0010" => SEG<="10100100"; 
			WHEN "0011" => SEG<="10110000"; 
			WHEN "0100" => SEG<="10011001"; 
			WHEN "0101" => SEG<="10010010"; 
			WHEN "0110" => SEG<="10000010"; 
			WHEN "0111" => SEG<="11111000"; 
			WHEN "1000" => SEG<="10000000"; 
			WHEN "1001" => SEG<="10010000"; 
			WHEN OTHERS => SEG<="11111111"; 
		END CASE;
		IF SCAN_COUNT = "010" OR
			SCAN_COUNT = "100"	THEN SEG(7)<='0';
		ELSE SEG(7)<='1';
		END IF;
	END PROCESS DECODE;  
	-- 3-8译码 片选
	SEL <=  "111110" WHEN SCAN_COUNT = "000" ELSE 
			  "111101" WHEN SCAN_COUNT = "001" ELSE 
			  "111011" WHEN SCAN_COUNT = "010" ELSE 
			  "110111" WHEN SCAN_COUNT = "011" ELSE 
			  "101111" WHEN SCAN_COUNT = "100" ELSE 
			  "011111" WHEN SCAN_COUNT = "101" ELSE 
			  "111111";
END BHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY shizhong IS
PORT(
CLK : IN STD_LOGIC;  -- 50Hz时钟信号输入
C_RESET : IN STD_LOGIC;  -- 时钟复位信号
C_SET_MIN, C_SET_HOUR : IN STD_LOGIC;  -- 时间调节
BUZZER : OUT STD_LOGIC;  -- 蜂鸣器控制
SEGMENT_SEL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);  -- 数码位选信号输出
SEGMENT_SEG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 数码管段选信号输出
FLASH_LED : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)  -- 流水灯
);
END shizhong;

ARCHITECTURE BHV OF shizhong IS
   -- 调用秒钟计数模块声明
	COMPONENT miaozhongjishuqi
	PORT(
	clk_to_second, reset, set_min : IN STD_LOGIC;
	CO : OUT STD_LOGIC;
	DATOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
	END COMPONENT;
	-- 调用分钟计数模块声明
	COMPONENT fenzhongjishuqi
	PORT(
	clk_to_minute, reset, set_hour : IN STD_LOGIC;
	CO : OUT STD_LOGIC;
	DATOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	-- 调用小时计数模块声明
	COMPONENT shizhongjishuqi
	PORT(clk_to_hour, reset : IN STD_LOGIC;
                                DATOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT;
	-- 调用译码显示模块声明
	COMPONENT xianshi
	PORT(            
	SCAN_CLK : IN STD_LOGIC;  -- 扫描时钟输入 
	HOUR, MINUTE, SECOND : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 时间数据输入
	SEL : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);  -- 位选信号输出								 
	SEG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));  -- 段选信号输出
	END COMPONENT;
	-- 调用分频模块声明
	COMPONENT fenpin
	PORT(				   CLK_50MHz : IN STD_LOGIC;
         CLK_1Hz, CLK_250Hz, CLK_500Hz, CLK_1000Hz : OUT STD_LOGIC);
	END COMPONENT;
	-- 按键延时消抖模块
	COMPONENT xiaodou
	PORT(CLK, KEY_IN : IN STD_LOGIC;  
			 KEY_OUT : OUT STD_LOGIC);
	END COMPONENT;
	--报时模块
	COMPONENT  baoshi  
	PORT(  CLK : IN STD_LOGIC;  -- 激励LED变化
			CLK500 : IN STD_LOGIC;
			CLK1000 : IN STD_LOGIC;
		  M_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 输入分钟显示数据 
		  S_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 输入秒钟显示数据 
	   SPEAKER : OUT STD_LOGIC;  -- 蜂鸣器控制
		   LED : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));  -- 流水灯
	END COMPONENT;
SIGNAL AD_HOUR, AD_MIN : STD_LOGIC;  -- 时钟调节信号
SIGNAL S_CO, M_CO : STD_LOGIC;  -- 计数进位
SIGNAL C_CLK, SCAN_CLK, FLOW_CLK, C_1000 : STD_LOGIC;  -- 计数时钟，扫描时钟，500,1000
SIGNAL S_DAT, M_DAT, H_DAT : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 秒，分，时显示数据
	BEGIN
		u1 : fenpin        	  PORT MAP(CLK, C_CLK, FLOW_CLK , SCAN_CLK, C_1000);  -- 分频1、250、500、1000
	   u2 : miaozhongjishuqi PORT MAP(C_CLK, C_RESET, AD_MIN, S_CO, S_DAT);  -- 秒钟
		u3 : fenzhongjishuqi PORT MAP(S_CO, C_RESET, AD_HOUR, M_CO, M_DAT);  -- 分钟
		u4 : shizhongjishuqi   PORT MAP(M_CO, C_RESET, H_DAT);  -- 小时
		u5 : xianshi          PORT MAP(SCAN_CLK, H_DAT, M_DAT, S_DAT, SEGMENT_SEL, SEGMENT_SEG);  -- 译码显示
		u6 : xiaodou        PORT MAP(SCAN_CLK, C_SET_MIN, AD_MIN);  -- 分钟调整
		u7 : xiaodou        PORT MAP(SCAN_CLK, C_SET_HOUR, AD_HOUR);  -- 小时调整
		u8 : baoshi         PORT MAP(C_CLK, SCAN_CLK, C_1000, M_DAT, S_DAT, BUZZER, FLASH_LED);  -- 整点报时
END BHV;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY baoshi IS
PORT(  CLK : IN STD_LOGIC;
		CLK500 : IN STD_LOGIC;
		CLK1000 : IN STD_LOGIC;
      M_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 输入分钟显示数据 
	  S_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  -- 输入秒钟显示数据 
   SPEAKER : OUT STD_LOGIC;  -- 蜂鸣器控制
	   LED : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));  -- 流水灯
END baoshi;

ARCHITECTURE BHV OF baoshi IS
SIGNAL SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL COUNT : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL COUNT1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN  
	REG : PROCESS(CLK) BEGIN
		IF CLK'EVENT AND CLK = '1'		THEN --1HZ
			IF COUNT < "111"	THEN COUNT <= COUNT + 1;
			ELSE COUNT <= "000"; 
			END IF;
		END IF;
	END PROCESS REG;
	FLOW : PROCESS(COUNT, M_IN, S_IN) BEGIN
		IF M_IN = "00000000"	AND S_IN < "00001001"	THEN  -- 整点闪烁10秒
			CASE COUNT IS
				WHEN "000" => LED <="1000";  
				WHEN "001" => LED <="0100";  
				WHEN "010" => LED <="0010";  
				WHEN "011" => LED <="0001";
				WHEN "111" => LED <="0010";	
				WHEN "101" => LED <="0100";
				WHEN "110" => LED <="1000";
				WHEN OTHERS => LED <="1111";
			END CASE;
		ELSE	LED <= "0000";
		END IF;
	END PROCESS FLOW;
	BEEP : PROCESS(COUNT1, M_IN, S_IN) BEGIN
		IF M_IN = "00000000"	AND S_IN = "0000000"  	THEN  -- 整点报时
			SPEAKER <=CLK1000;
		ELSE
			SPEAKER <='1';
		END IF;
		IF M_IN = "01011001"		THEN
			IF S_IN = "01010000" OR --0
			S_IN = "01010010" OR --2
			S_IN = "01010100" OR --4
			S_IN = "01010110" OR --6
			S_IN = "01011000" THEN --8
				SPEAKER <=CLK500;
			ELSE 
				SPEAKER <='1';
			END IF;
		END IF;
	END PROCESS BEEP;
END BHV;