CPU设计实战：Loongarch版实践任务8：阻塞技术解决相关引发的冲突

YSJ_536

已于 2024-06-05 13:28:38 修改

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文章标签： fpga开发

于 2024-06-05 13:25:42 首次发布

本文链接：https://blog.csdn.net/m0_65369544/article/details/139433090

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好的，设计完简单的流水线之后，看看下个任务是什么吧。看完之后是让我们解决流水线之间指令引起的冲突。

以下解释来源于胡伟武老师的计算机体系结构基础

什么是指令引起的冲突呢？指令的相关大致可以分为3类：数据相关、控制相关和结构相关，而这个实验就是解决数据相关的引起的冲突，根据冲突访问读和写的次序可以分为3种。第1种是写后读（Read After Write,简称RAW）相关，即后面指令要用到前面指令所写的数据，也称为真相关。第2种是写后写（Write After Write,简称WAW）相关，即两条指令写同一个单元，也称为输出相关。第3种是读后写（Write After Read,简称WAR）相关，即后面的指令覆盖前面指令所读的单元，也称为反相关。而在5级简单流水线中，只有RAW相关会引起流水线冲突，WAR相关和WAW相关不会引起流水线冲突。

对于如下指令序列

其中第1、2条指令间，第2、3条指令间，第3、4条指令间存在RAW相关。

从第1条指令的写回阶段指向第2条指令的译码阶段的箭头以及从第2条指令的写回阶段指向第3条指令的译码阶段的箭头都表示RAW相关会引起冲突。这是因为如果第2条指令要使用第1条指令写回到寄存器的结果，就必须保证第2条指令读取寄存器的时候第1条指令的结果已经写回到寄存器中了，而现有的5级流水线结构如果不加控制，第2条指令就会在第1条指令写回寄存器之前读取寄存器，从而引发数据错误。为了保证执行的正确，一种最直接的解决方式是让第2条指令在译码阶段等待（阻塞）3拍，直到第1条指令将结果写入寄存器后才能读取寄存器，进入后续的执行阶段。同样的方式亦适用于第2、3条指令之间和第3、4条指令之间。

而具体该如何做呢？结合上面的解释可以这么做：处于译码流水级的指令具有来自非0号寄存器的源操作数，如果这些源操作数中的任何一个寄存器号与当前时刻处于执行、访存或写回阶段的指令的目的操作数的寄存器号相同，则表明会引发冲突的写后读相关关系。

并且有一个细节：保证被比较的两个寄存器号都是有效的，这体现在三个方面：1.参与比较的指令到底有没有寄存器的源操作数或者目的操作数，2.如果寄存器号为0，那么也不用进行比较，因为0号寄存器的值恒为0，3.用来比较的流水级上到底有没有指令，如果没有指令那么比较毫无意义。

在判断条件成立的时候，将ID阶段的ready_go信号进行调整即可。

在写后读相关存在一种情况——LOAD TO BRANCH，即load后紧跟branch指令，而转移指令至少有一个源寄存器与load指令目的寄存器相同，所以存在写后读相关，在这种情况下的冲突引起的原因叫做“转移计算未完成”此时的brbus产生的nextPC肯定是不对的，所以我们要在上面新增一个brstall，表示转移计算未完成，另外也要给preIF加上ready_go，当brstall为1时，置ready_go为0。

另外在转移计算未完成时，建议将控制指令ram的使能信号拉低使之无效，在后续引入总线设计的时候，没有注意到这一点的话会很容易出错。

在改我代码的时候解决延迟槽就解决了好久，因为loongarch是没有延迟槽的，需要想办法把跳转指令后面的指令不去处理，主要就是跳转指令这一块引起的冲突，老是差一两个周期导致整个流水线停止，最终也是改好了。

下面三个是改动了的module

IF stage


module IF_stage(
	input  clk,
	input  reset,
	input  ID_allow_in,
	input  [33:0] br_bus,
	output        inst_sram_en,
    output [ 3:0] inst_sram_we,
    output [31:0] inst_sram_addr,
    output [31:0] inst_sram_wdata,
    input  [31:0] inst_sram_rdata,
	output [63:0] IF_ID_bus,
	output IF_to_ID_valid

    );
wire br_stall;
wire br_taken;
wire [31:0] br_target;
wire [31:0] IF_inst;
reg  [31:0] IF_pc;
wire [31:0] seq_pc;
wire [31:0] nextpc;
wire pre_If_ready_go;
wire IF_ready_go;
wire IF_allow_in;
wire to_IF_valid;
wire IF_to_ID_valid;
reg  IF_valid;


assign pre_If_ready_go = ~br_stall;
assign to_IF_valid = ~reset && pre_If_ready_go;
assign IF_ready_go = 1'b1;
assign IF_allow_in = !IF_valid || IF_ready_go && ID_allow_in;
assign IF_to_ID_valid =  IF_valid && IF_ready_go;   
assign IF_ID_bus = {IF_pc, IF_inst};
assign {br_stall,br_taken, br_target} = br_bus;

	always @(posedge clk) begin
	    if (reset) begin
	        IF_valid <= 1'b0;
	        
	    end
	    else if (IF_allow_in) begin
	        IF_valid <= to_IF_valid;
	    end
	end

	always @(posedge clk) begin 
		if(reset) begin
			 IF_pc <= 32'h1bfffffc;
			
		end else if(to_IF_valid && (IF_allow_in))begin
			 IF_pc <= nextpc;		
		end
	end
                       

assign seq_pc       = IF_pc + 3'h4;
assign nextpc       = br_taken ? br_target : seq_pc;
assign inst_sram_en    = to_IF_valid && (IF_allow_in || br_stall);
assign inst_sram_addr = nextpc;
assign IF_inst = inst_sram_rdata;
assign inst_sram_we = 4'b0;
assign inst_sram_wdata = 32'b0;


endmodule

ID stage

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/05/29 10:44:41
// Design Name: 
// Module Name: ID_stage
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module ID_stage(
  input  clk,
  input  reset,
  input  EX_allow_in,
  input  IF_to_ID_valid,
  input  [63:0]IF_ID_bus,
  input  [37:0]WB_rf_bus,
  input  [ 4:0]EX_dest,
  input  [ 4:0]MEM_dest,
  input  [ 4:0]WB_dest,
  input  EX_load,
  output ID_allow_in,
  output [33:0]br_bus,
  output [150:0]ID_EX_bus,
  output ID_to_EX_valid,
  output to_EX_inst_bl

    );
reg  [31:0] ID_pc;
reg  [31:0] ID_inst;
reg  ID_valid;
wire ID_ready_go;
reg delay_slot;

wire [31:0] br_offs;
wire [31:0] jirl_offs;
wire        src_reg_is_rd;
wire        src_reg_is_rj;
wire        src_reg_is_rk;
wire        dst_is_r1;
wire [ 5:0] op_31_26;
wire [ 3:0] op_25_22;
wire [ 1:0] op_21_20;
wire [ 4:0] op_19_15;
wire [ 4:0] rd;
wire [ 4:0] rj;
wire [ 4:0] rk;
wire [11:0] i12;
wire [19:0] i20;
wire [15:0] i16;
wire [25:0] i26;

wire rf_we  ;
wire [4:0]rf_waddr;
wire [31:0]rf_wdata;
wire [4:0]rf_raddr1;
wire [31:0]rf_rdata1;
wire [4:0]rf_raddr2;
wire [31:0]rf_rdata2;

wire [11:0] alu_op;
wire        src1_is_pc;
wire        src2_is_imm;
wire        src2_is_4;
wire        res_from_mem;
wire        gr_we;
wire        mem_we;
wire [4: 0] dest;
wire [31:0] rj_value;
wire [31:0] rkd_value;
wire [31:0] imm;

wire br_stall;
wire br_taken;
wire [31:0]br_target;

wire [63:0] op_31_26_d;
wire [15:0] op_25_22_d;
wire [ 3:0] op_21_20_d;
wire [31:0] op_19_15_d;

wire        inst_add_w;
wire        inst_sub_w;
wire        inst_slt;
wire        inst_sltu;
wire        inst_nor;
wire        inst_and;
wire        inst_or;
wire        inst_xor;
wire        inst_slli_w;
wire        inst_srli_w;
wire        inst_srai_w;
wire        inst_addi_w;
wire        inst_ld_w;
wire        inst_st_w;
wire        inst_jirl;
wire        inst_b;
wire        inst_bl;
wire        inst_beq;
wire        inst_bne;
wire        inst_lu12i_w;

wire        need_ui5;
wire        need_si12;
wire        need_si16;
wire        need_si20;
wire        need_si26;

wire [31:0]alu_src1;
wire [31:0]alu_src2;


assign op_31_26  = ID_inst[31:26];
assign op_25_22  = ID_inst[25:22];
assign op_21_20  = ID_inst[21:20];
assign op_19_15  = ID_inst[19:15];

assign rd   = ID_inst[ 4: 0];
assign rj   = ID_inst[ 9: 5];
assign rk   = ID_inst[14:10];

wire same_rj;
wire same_rk;
wire same_rd;
wire inst_no_dest_reg;
assign same_rd = src_reg_is_rd && rd != 5'b0 &&((rd == EX_dest) || (rd == MEM_dest) || (rd == WB_dest)); 
assign same_rj = src_reg_is_rj && rj != 5'b0 &&((rj == EX_dest) || (rj == MEM_dest) || (rj == WB_dest)); 
assign same_rk = src_reg_is_rk && rk != 5'b0 &&((rk == EX_dest) || (rk == MEM_dest) || (rk == WB_dest)); 
assign inst_no_dest_reg = inst_st_w | inst_b | inst_beq | inst_bne;
assign block = same_rd || same_rj || same_rk;
assign i12  = ID_inst[21:10];
assign i20  = ID_inst[24: 5];
assign i16  = ID_inst[25:10];
assign i26  = {ID_inst[ 9: 0], ID_inst[25:10]};


decoder_6_64 u_dec0(.in(op_31_26 ), .out(op_31_26_d ));
decoder_4_16 u_dec1(.in(op_25_22 ), .out(op_25_22_d ));
decoder_2_4  u_dec2(.in(op_21_20 ), .out(op_21_20_d ));
decoder_5_32 u_dec3(.in(op_19_15 ), .out(op_19_15_d ));

assign inst_add_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h00];
assign inst_sub_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h02];
assign inst_slt    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h04];
assign inst_sltu   = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h05];
assign inst_nor    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h08];
assign inst_and    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h09];
assign inst_or     = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0a];
assign inst_xor    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0b];
assign inst_slli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h01];
assign inst_srli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h09];
assign inst_srai_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h11];
assign inst_addi_w = op_31_26_d[6'h00] & op_25_22_d[4'ha];
assign inst_ld_w   = op_31_26_d[6'h0a] & op_25_22_d[4'h2];
assign inst_st_w   = op_31_26_d[6'h0a] & op_25_22_d[4'h6];
assign inst_jirl   = op_31_26_d[6'h13];
assign inst_b      = op_31_26_d[6'h14];
assign inst_bl     = op_31_26_d[6'h15];
assign inst_beq    = op_31_26_d[6'h16];
assign inst_bne    = op_31_26_d[6'h17];
assign inst_lu12i_w= op_31_26_d[6'h05] & ~ID_inst[25];

assign to_EX_inst_bl = inst_bl;

assign alu_op[ 0] = inst_add_w | inst_addi_w | inst_ld_w | inst_st_w
                    | inst_jirl | inst_bl;
assign alu_op[ 1] = inst_sub_w;
assign alu_op[ 2] = inst_slt;
assign alu_op[ 3] = inst_sltu;
assign alu_op[ 4] = inst_and;
assign alu_op[ 5] = inst_nor;
assign alu_op[ 6] = inst_or;
assign alu_op[ 7] = inst_xor;
assign alu_op[ 8] = inst_slli_w;
assign alu_op[ 9] = inst_srli_w;
assign alu_op[10] = inst_srai_w;
assign alu_op[11] = inst_lu12i_w;

assign need_ui5   =  inst_slli_w | inst_srli_w | inst_srai_w;
assign need_si12  =  inst_addi_w | inst_ld_w | inst_st_w;
assign need_si16  =  inst_jirl | inst_beq | inst_bne;
assign need_si20  =  inst_lu12i_w;
assign need_si26  =  inst_b | inst_bl;
assign src2_is_4  =  inst_jirl | inst_bl;
assign imm = src2_is_4 ? 32'h4                      :
             need_si20 ? {i20[19:0], 12'b0}         :
/*need_ui5 || need_si12*/{{20{i12[11]}}, i12[11:0]} ;

assign br_offs = need_si26 ? {{ 4{i26[25]}}, i26[25:0], 2'b0} :
                             {{14{i16[15]}}, i16[15:0], 2'b0} ;

assign jirl_offs = {{14{i16[15]}}, i16[15:0], 2'b0};

assign src_reg_is_rd = inst_beq | inst_bne | inst_st_w;
assign src_reg_is_rj = ~(inst_b | inst_bl | inst_lu12i_w);
assign src_reg_is_rk = ~(inst_slli_w | inst_srli_w | inst_srai_w | inst_addi_w | inst_ld_w | inst_st_w | inst_jirl | 
                      inst_b | inst_bl | inst_beq | inst_bne | inst_lu12i_w);
assign src1_is_pc    = inst_jirl | inst_bl;

assign src2_is_imm   = inst_slli_w |
                       inst_srli_w |
                       inst_srai_w |
                       inst_addi_w |
                       inst_ld_w   |
                       inst_st_w   |
                       inst_lu12i_w|
                       inst_jirl   |
                       inst_bl     ;

assign res_from_mem  = inst_ld_w;
assign dst_is_r1     = inst_bl;
assign gr_we         = ~inst_st_w & ~inst_beq & ~inst_bne & ~inst_b;
assign mem_we        = inst_st_w;
assign dest          = inst_no_dest_reg ? 5'b0 :
                                        dst_is_r1 ? 5'd1 : rd;

assign rf_raddr1 = rj;
assign rf_raddr2 = src_reg_is_rd ? rd :rk;

assign {rf_we, rf_waddr, rf_wdata} = WB_rf_bus;

regfile u_regfile(
    .clk    (clk      ),
    .raddr1 (rf_raddr1),
    .rdata1 (rf_rdata1),
    .raddr2 (rf_raddr2),
    .rdata2 (rf_rdata2),
    .we     (rf_we    ),
    .waddr  (rf_waddr ),
    .wdata  (rf_wdata )
    );

assign rj_value  = rf_rdata1;
assign rkd_value = rf_rdata2;

assign ID_EX_bus = {
                    ID_pc,//150:119
                    alu_op,//118:107
                    src2_is_4,//106
                    src1_is_pc,//105
                    src2_is_imm,//104
                    gr_we,//103
                    mem_we,//102
                    dest,//101:97
                    imm,//96:65
                    rj_value,//64:33
                    rkd_value,//32:1
                    res_from_mem //0:0
};
assign rj_eq_rd = (rj_value == rkd_value);
assign br_taken = (   inst_beq  &&  rj_eq_rd
                   || inst_bne  && !rj_eq_rd
                   || inst_jirl
                   || inst_bl
                   || inst_b
                  ) && ID_valid && !delay_slot;
assign br_target = (inst_beq || inst_bne || inst_bl || inst_b) ? (ID_pc + br_offs) :
                                                   /*inst_jirl*/ (rj_value + jirl_offs);
assign br_bus = {
                br_stall, //33
                br_taken,//32
                br_target //31:0
                };
assign br_stall = br_taken && EX_load && ID_valid;
assign ID_ready_go    = ~block;
assign ID_allow_in     = !ID_valid || ID_ready_go && EX_allow_in;
assign ID_to_EX_valid = ID_valid && ID_ready_go && !delay_slot;
always @(posedge clk) begin
    if (reset) begin
        ID_valid <= 1'b0;
        delay_slot <= 1'b0;
    end
    else if (ID_allow_in) begin
        ID_valid <= IF_to_ID_valid;
    end
 
    if (IF_to_ID_valid && ID_allow_in) begin
        {ID_pc,ID_inst} <= IF_ID_bus;
         if (br_taken) begin
          delay_slot <= 1'b1;
          end else begin
            delay_slot <=1'b0;
          end
    end

end


endmodule

EX stage

module EX_stage(
    input         clk,
    input         reset,
    input  MEM_allow_in,
    input  ID_to_EX_valid,
    output EX_allow_in,
    input  [150:0]ID_EX_bus,
    input   inst_bl,
    output [70:0]EX_MEM_bus,
    output  EX_to_MEM_valid,
    output        data_sram_en,
    output [ 3:0] data_sram_we,
    output [31:0] data_sram_addr,
    output [31:0] data_sram_wdata,
    output [ 4:0] EX_dest_reg,
    output EX_load
    );

    reg  [31:0] EX_pc;

    reg EX_valid;
    wire EX_ready_go;
    reg  [11:0] EX_alu_op;
    reg         EX_src1_is_pc;
    reg         EX_src2_is_imm;
    reg         EX_src2_is_4;
    reg         EX_res_from_mem;
    reg         EX_gr_we;
    reg         EX_mem_we;
    reg  [4: 0] EX_dest;
    reg  [31:0] EX_rj_value;
    reg  [31:0] EX_rkd_value;
    reg  [31:0] EX_imm;
    wire [31:0] alu_result;
    reg EX_inst_bl;
    wire [31:0] alu_src1;
    wire [31:0] alu_src2;
    assign EX_ready_go    = 1'b1;
    assign EX_allow_in     = !EX_valid || EX_ready_go && MEM_allow_in;
    assign EX_to_MEM_valid =  EX_valid && EX_ready_go;
    assign EX_MEM_bus = {
                        EX_pc,//70:39
                        EX_gr_we,//38
                        EX_dest,//37:33
                        alu_result,//32:1
                        EX_res_from_mem//0
    };
    assign EX_dest_reg = EX_dest & {5{EX_valid}};
always @(posedge clk) begin
    if (reset) begin
        EX_valid <= 1'b0;
    end
    else if (EX_allow_in) begin
        EX_valid <= ID_to_EX_valid;
    end

    if (ID_to_EX_valid && EX_allow_in) begin
        {EX_pc ,
        EX_alu_op ,
        EX_src2_is_4,
        EX_src1_is_pc,
        EX_src2_is_imm,
        EX_gr_we,
        EX_mem_we,
        EX_dest,
        EX_imm,
        EX_rj_value,
        EX_rkd_value,
        EX_res_from_mem} <= ID_EX_bus;
        EX_inst_bl <= inst_bl;
    end
end
assign EX_load = EX_res_from_mem;
alu u_alu(
    .alu_op     (EX_alu_op ),
    .alu_src1   (alu_src1  ),
    .alu_src2   (alu_src2  ),
    .alu_result (alu_result)
    );
assign alu_src1 = EX_src1_is_pc  ? EX_pc : EX_rj_value;
assign alu_src2 = EX_src2_is_imm ? EX_imm : (EX_inst_bl ? 32'd4 : EX_rkd_value);
assign data_sram_en = 1'b1;
assign data_sram_we    = EX_mem_we && EX_valid ? 4'b1111 : 4'b0000;
assign data_sram_addr  = alu_result;
assign data_sram_wdata = EX_rkd_value;

endmodule

MEM stage

module MEM_stage(
    input  clk,
    input  reset,
    input  WB_allow_in,
    output MEM_allow_in,
    input  [70:0]EX_MEM_bus,
    input  [31:0] data_sram_rdata,
    input  EX_to_MEM_valid, 
    output MEM_to_WB_valid,
    output [69:0]MEM_WB_bus,
    output [ 4:0]MEM_dest_reg
    );

reg [31:0] MEM_pc;
reg MEM_res_from_mem;
reg MEM_gr_we;
reg [4:0]MEM_dest;
reg [31:0]MEM_alu_result;
wire [31:0] MEM_final_result;
wire [31:0] MEM_result;

reg MEM_valid;
wire MEM_ready_go;
assign MEM_ready_go    = 1'b1;
assign MEM_allow_in     = !MEM_valid || MEM_ready_go && WB_allow_in;
assign MEM_to_WB_valid = MEM_valid && MEM_ready_go;
assign MEM_dest_reg = MEM_dest & {5{MEM_valid}};
always @(posedge clk) begin
    if (reset) begin
        MEM_valid <= 1'b0;
    end
    else if (MEM_allow_in) begin
        MEM_valid <= EX_to_MEM_valid;
    end

    if (EX_to_MEM_valid && MEM_allow_in) begin
        {MEM_pc ,
        MEM_gr_we ,
        MEM_dest,
        MEM_alu_result,
        MEM_res_from_mem } <= EX_MEM_bus;
    end
end
assign MEM_result = data_sram_rdata;
assign MEM_final_result = MEM_res_from_mem ? MEM_result : MEM_alu_result;
assign MEM_WB_bus = {
                        MEM_pc,//69:38
                        MEM_gr_we,//37
                        MEM_dest,// 36:32
                        MEM_final_result//31:0
};
endmodule

WB stage

module WB_stage(
  input  clk,
  input  reset,
  output WB_allow_in,
  input  MEM_to_WB_valid,
  input  [69:0] MEM_WB_bus,
  output [37:0] WB_rf_bus,
  output [31:0] debug_wb_pc,
  output [ 3:0] debug_wb_rf_we,
  output [ 4:0] debug_wb_rf_wnum,
  output [31:0] debug_wb_rf_wdata,
  output [ 4:0] WB_dest_reg
  );
reg [31:0] WB_pc;
reg WB_valid;
wire WB_ready_go;

reg WB_gr_we;
reg [4:0]WB_dest;
reg [31:0]WB_final_result;
wire rf_we   ;
wire [4:0]rf_waddr;
wire [31:0]rf_wdata;
assign WB_ready_go = 1'b1;
assign WB_allow_in  = !WB_valid || WB_ready_go;
assign WB_dest_reg = WB_dest & {5{WB_valid}};
always @(posedge clk) begin
    if (reset) begin
        WB_valid <= 1'b0;
    end
    else if (WB_allow_in) begin
        WB_valid <= MEM_to_WB_valid;
    end

    if (MEM_to_WB_valid && WB_allow_in) begin
      {WB_pc,
       WB_gr_we,
       WB_dest,
       WB_final_result} <= MEM_WB_bus;
       
    end
end

assign rf_we    = WB_gr_we && WB_valid;
assign rf_waddr = WB_dest;
assign rf_wdata = WB_final_result;

assign WB_rf_bus = {rf_we,//37
                    rf_waddr,//36:32
                    rf_wdata//31:0
                    };

assign debug_wb_pc       = rf_we ? WB_pc : debug_wb_pc;
assign debug_wb_rf_we   = {4{rf_we}};
assign debug_wb_rf_wnum  = WB_valid && rf_we ? WB_dest : debug_wb_rf_wnum;
assign debug_wb_rf_wdata = WB_valid && rf_we ? WB_final_result : debug_wb_rf_wdata;


endmodule

mycpu

module mycpu_top(
    input  wire        clk,
    input  wire        resetn,
    // inst sram interface
    output wire        inst_sram_en,
    output wire [ 3:0] inst_sram_we,
    output wire [31:0] inst_sram_addr,
    output wire [31:0] inst_sram_wdata,
    input  wire [31:0] inst_sram_rdata,
    // data sram interface
    output wire        data_sram_en,
    output wire [ 3:0] data_sram_we,
    output wire [31:0] data_sram_addr,
    output wire [31:0] data_sram_wdata,
    input  wire [31:0] data_sram_rdata,
    // trace debug interface
    output wire [31:0] debug_wb_pc,
    output wire [ 3:0] debug_wb_rf_we,
    output wire [ 4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata
);
reg         reset;
always @(posedge clk) reset <= ~resetn;



// allow_in
wire ID_allow_in;
wire EX_allow_in;
wire MEM_allow_in;
wire WB_allow_in;
//bus
wire [63:0]IF_ID_bus;
wire [150:0]ID_EX_bus;
wire [70:0]EX_MEM_bus;
wire [69:0]MEM_WB_bus;
wire [33:0]br_bus;
wire [37:0]WB_rf_bus;
//valid
wire IF_to_ID_valid;
wire ID_to_EX_valid;
wire EX_to_MEM_valid;
wire MEM_to_WB_valid;
//inst_bl
wire inst_bl;

//block
wire EX_load;
wire [4:0]EX_dest;
wire [4:0]MEM_dest;
wire [4:0]WB_dest;
IF_stage IF(
    .clk(clk),
    .reset(reset),
    .ID_allow_in(ID_allow_in),
    .br_bus(br_bus),
    .inst_sram_en(inst_sram_en),
    .inst_sram_we(inst_sran_we),
    .inst_sram_addr(inst_sram_addr),
    .inst_sram_wdata(inst_sram_wdata),
    .inst_sram_rdata(inst_sram_rdata),
    .IF_ID_bus(IF_ID_bus),
    .IF_to_ID_valid(IF_to_ID_valid)

    );
ID_stage ID(
   .clk(clk),
   .reset(reset),
   .EX_allow_in(EX_allow_in),
   .IF_to_ID_valid(IF_to_ID_valid),
   .IF_ID_bus(IF_ID_bus),
   .WB_rf_bus(WB_rf_bus),
   .ID_allow_in(ID_allow_in),
   .br_bus(br_bus),
   .ID_EX_bus(ID_EX_bus),
   .ID_to_EX_valid(ID_to_EX_valid),
   .to_EX_inst_bl(inst_bl),
   .EX_dest(EX_dest),
   .WB_dest(WB_dest),
   .MEM_dest(MEM_dest),
   .EX_load(EX_load)
    );
EX_stage EX(
    .clk(clk),
    .reset(reset),
    .MEM_allow_in(MEM_allow_in),
    .ID_to_EX_valid(ID_to_EX_valid),
    .EX_allow_in(EX_allow_in),
    .ID_EX_bus(ID_EX_bus),
    .inst_bl(inst_bl),
    .EX_MEM_bus(EX_MEM_bus),
    .EX_to_MEM_valid(EX_to_MEM_valid),
    .data_sram_en(data_sram_en),
    .data_sram_we(data_sram_we),
    .data_sram_addr(data_sram_addr),
    .data_sram_wdata(data_sram_wdata),
    .EX_dest_reg(EX_dest),
    .EX_load(EX_load)
);
MEM_stage MEM(
    .clk(clk),
    .reset(reset),
    .WB_allow_in(WB_allow_in),
    .MEM_allow_in(MEM_allow_in),
    .EX_MEM_bus(EX_MEM_bus),
    .data_sram_rdata(data_sram_rdata),
    .EX_to_MEM_valid(EX_to_MEM_valid),    
    .MEM_to_WB_valid(MEM_to_WB_valid),
    .MEM_WB_bus(MEM_WB_bus),
    .MEM_dest_reg(MEM_dest)
    );
WB_stage WB(
    .clk(clk),
    .reset(reset),
    .WB_allow_in(WB_allow_in),
    .MEM_to_WB_valid(MEM_to_WB_valid),
    .MEM_WB_bus(MEM_WB_bus),
    .WB_rf_bus(WB_rf_bus),
    .debug_wb_pc(debug_wb_pc) ,
    .debug_wb_rf_we(debug_wb_rf_we),
    .debug_wb_rf_wnum(debug_wb_rf_wnum),
    .debug_wb_rf_wdata(debug_wb_rf_wdata),
    .WB_dest_reg(WB_dest)
    );
endmodule