CPU设计实战：Loongarch版 lab7：不考虑相关冲突处理的简单流水线CPU

首先上来看到了这两句话，那么直接起手改变一下接口

    // inst sram interface
    output wire         inst_sram_en,
    output wire [ 3:0] inst_sram_we,
    output wire [31:0] inst_sram_addr,
    output wire [31:0] inst_sram_wdata,
    input  wire [31:0] inst_sram_rdata,
    // data sram interface
    output wire         data_sram_en,
    output wire [ 3:0] data_sram_we,
    output wire [31:0] data_sram_addr,
    output wire [31:0] data_sram_wdata,
    input  wire [31:0] data_sram_rdata,

ok，添加完成后先进行运行，看看报错在什么地方（舔舌）。

直接出来这个了，我滴妈，难道，我滴任务完成辣？nonono，一看输出全为0，显然不是的，再查下去发现指令ram使能信号一直高阻态，好嘛，那大致明白要干什么了，那就要把mycpu的单周期改为流水线再来看看怎么事吧。这里借用了龙芯团队胡伟武老师等人编写的计算机体系结构基础的一些图。

然后流水线的设计参考汪文祥工程师等人攥写的CPU设计实战，引入了同步ram，所以考虑采用nextpc作为指令ram的读地址（视作pre-IF），并且要注意设置好各级流水线之间的握手信号。

或者还有一种方案是在IF阶段请求读指令ram，然后在ID阶段获取到指令，我第一次分割时候是这样做的，但是实现完之后一直会有一些小bug，改起来比较头疼，于是换了上面的方案。

我在一开始将每个需要传递到下一个阶段的信号都写在输入输出那里，发现这在我后面连线时会变得异常麻烦，参考了openla500后发现可以简化一下，于是就设置了每级流水之间的bus，会让连线变得简单一点。

我认为在了解了怎么将单周期分割成流水线之后最主要就是要细心了，将mycpu分成5个module之后，有时候会出现丢掉几个赋值语句（在ctrl+C和ctrl+V时）或者是数据位宽的问题，比如我就忘掉了数据ram的使能信号和读出数据的赋值，导致我卡了很久，而且在复制的时候我认为要给不同阶段之间传递的需要保持的信号附上不同的名字，这样就可以知道是哪个阶段出了问题。不过最终也是解决了问题，通过测试。

IF stage

module IF_stage(
	input  clk,
	input  reset,
	input  ID_allow_in,
	input  [32:0] br_bus,
	output        inst_sram_en,
    output [ 3:0] inst_sram_we,
    output [31:0] inst_sram_addr,
    output [31:0] inst_sram_wdata,
    input  [31:0] inst_sram_rdata,
	output [63:0] IF_ID_bus,
	output IF_to_ID_valid

    );
wire br_taken;
wire [31:0] br_target;
wire [31:0] IF_inst;
reg  [31:0] IF_pc;
wire [31:0] seq_pc;
wire [31:0] nextpc;
wire IF_ready_go;
wire IF_allow_in;
wire to_IF_valid;
wire IF_to_ID_valid;
reg  IF_valid;

assign to_IF_valid = ~reset;
assign IF_ready_go = 1'b1;
assign IF_allow_in = !IF_valid || IF_ready_go && ID_allow_in;
assign IF_to_ID_valid =  IF_valid && IF_ready_go;   
assign IF_ID_bus = {IF_pc, IF_inst};
assign {br_taken, br_target} = br_bus;

	always @(posedge clk) begin
	    if (reset) begin
	        IF_valid <= 1'b0;
	    end
	    else if (IF_allow_in) begin
	        IF_valid <= to_IF_valid;
	    end
	end

	always @(posedge clk) begin 
		if(reset) begin
			 IF_pc <= 32'h1bfffffc;
		end else begin
			 IF_pc <= nextpc;			
		end
	end
                       

assign seq_pc       = IF_pc + 3'h4;
assign nextpc       = br_taken ? br_target : seq_pc;
assign inst_sram_en    = to_IF_valid && IF_allow_in;
assign inst_sram_addr = nextpc;
assign IF_inst = inst_sram_rdata;
assign inst_sram_we = 4'b0;
assign inst_sram_wdata = 32'b0;


endmodule

ID stage

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/05/29 10:44:41
// Design Name: 
// Module Name: ID_stage
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//
 
 
module ID_stage(
  input  clk,
  input  reset,
  input  EX_allow_in,
  input  IF_to_ID_valid,
  input  [63:0]IF_ID_bus,
  input  [37:0]WB_rf_bus,
  output ID_allow_in,
  output [32:0]br_bus,
  output [150:0]ID_EX_bus,
  output ID_to_EX_valid,
  output to_EX_inst_bl
 
    );
reg  [31:0] ID_pc;
reg  [31:0] ID_inst;
reg  ID_valid;
wire ID_ready_go;
reg delay_slot; 
 
wire [31:0] br_offs;
wire [31:0] jirl_offs;
wire        src_reg_is_rd;
wire        dst_is_r1;
wire [ 5:0] op_31_26;
wire [ 3:0] op_25_22;
wire [ 1:0] op_21_20;
wire [ 4:0] op_19_15;
wire [ 4:0] rd;
wire [ 4:0] rj;
wire [ 4:0] rk;
wire [11:0] i12;
wire [19:0] i20;
wire [15:0] i16;
wire [25:0] i26;
 
wire rf_we  ;
wire [4:0]rf_waddr;
wire [31:0]rf_wdata;
wire [4:0]rf_raddr1;
wire [31:0]rf_rdata1;
wire [4:0]rf_raddr2;
wire [31:0]rf_rdata2;
 
wire [11:0] alu_op;
wire        src1_is_pc;
wire        src2_is_imm;
wire        src2_is_4;
wire        res_from_mem;
wire        gr_we;
wire        mem_we;
wire [4: 0] dest;
wire [31:0] rj_value;
wire [31:0] rkd_value;
wire [31:0] imm;
 
wire br_taken;
wire [31:0]br_target;
 
wire [63:0] op_31_26_d;
wire [15:0] op_25_22_d;
wire [ 3:0] op_21_20_d;
wire [31:0] op_19_15_d;
 
wire        inst_add_w;
wire        inst_sub_w;
wire        inst_slt;
wire        inst_sltu;
wire        inst_nor;
wire        inst_and;
wire        inst_or;
wire        inst_xor;
wire        inst_slli_w;
wire        inst_srli_w;
wire        inst_srai_w;
wire        inst_addi_w;
wire        inst_ld_w;
wire        inst_st_w;
wire        inst_jirl;
wire        inst_b;
wire        inst_bl;
wire        inst_beq;
wire        inst_bne;
wire        inst_lu12i_w;
 
wire        need_ui5;
wire        need_si12;
wire        need_si16;
wire        need_si20;
wire        need_si26;
 
wire [31:0]alu_src1;
wire [31:0]alu_src2;
 
assign op_31_26  = ID_inst[31:26];
assign op_25_22  = ID_inst[25:22];
assign op_21_20  = ID_inst[21:20];
assign op_19_15  = ID_inst[19:15];
 
assign rd   = ID_inst[ 4: 0];
assign rj   = ID_inst[ 9: 5];
assign rk   = ID_inst[14:10];
 
assign i12  = ID_inst[21:10];
assign i20  = ID_inst[24: 5];
assign i16  = ID_inst[25:10];
assign i26  = {ID_inst[ 9: 0], ID_inst[25:10]};
 
 
decoder_6_64 u_dec0(.in(op_31_26 ), .out(op_31_26_d ));
decoder_4_16 u_dec1(.in(op_25_22 ), .out(op_25_22_d ));
decoder_2_4  u_dec2(.in(op_21_20 ), .out(op_21_20_d ));
decoder_5_32 u_dec3(.in(op_19_15 ), .out(op_19_15_d ));
 
assign inst_add_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h00];
assign inst_sub_w  = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h02];
assign inst_slt    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h04];
assign inst_sltu   = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h05];
assign inst_nor    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h08];
assign inst_and    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h09];
assign inst_or     = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0a];
assign inst_xor    = op_31_26_d[6'h00] & op_25_22_d[4'h0] & op_21_20_d[2'h1] & op_19_15_d[5'h0b];
assign inst_slli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h01];
assign inst_srli_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h09];
assign inst_srai_w = op_31_26_d[6'h00] & op_25_22_d[4'h1] & op_21_20_d[2'h0] & op_19_15_d[5'h11];
assign inst_addi_w = op_31_26_d[6'h00] & op_25_22_d[4'ha];
assign inst_ld_w   = op_31_26_d[6'h0a] & op_25_22_d[4'h2];
assign inst_st_w   = op_31_26_d[6'h0a] & op_25_22_d[4'h6];
assign inst_jirl   = op_31_26_d[6'h13];
assign inst_b      = op_31_26_d[6'h14];
assign inst_bl     = op_31_26_d[6'h15];
assign inst_beq    = op_31_26_d[6'h16];
assign inst_bne    = op_31_26_d[6'h17];
assign inst_lu12i_w= op_31_26_d[6'h05] & ~ID_inst[25];
 
assign to_EX_inst_bl = inst_bl;
 
assign alu_op[ 0] = inst_add_w | inst_addi_w | inst_ld_w | inst_st_w
                    | inst_jirl | inst_bl;
assign alu_op[ 1] = inst_sub_w;
assign alu_op[ 2] = inst_slt;
assign alu_op[ 3] = inst_sltu;
assign alu_op[ 4] = inst_and;
assign alu_op[ 5] = inst_nor;
assign alu_op[ 6] = inst_or;
assign alu_op[ 7] = inst_xor;
assign alu_op[ 8] = inst_slli_w;
assign alu_op[ 9] = inst_srli_w;
assign alu_op[10] = inst_srai_w;
assign alu_op[11] = inst_lu12i_w;
 
assign need_ui5   =  inst_slli_w | inst_srli_w | inst_srai_w;
assign need_si12  =  inst_addi_w | inst_ld_w | inst_st_w;
assign need_si16  =  inst_jirl | inst_beq | inst_bne;
assign need_si20  =  inst_lu12i_w;
assign need_si26  =  inst_b | inst_bl;
assign src2_is_4  =  inst_jirl | inst_bl;
assign imm = src2_is_4 ? 32'h4                      :
             need_si20 ? {i20[19:0], 12'b0}         :
/*need_ui5 || need_si12*/{{20{i12[11]}}, i12[11:0]} ;
 
assign br_offs = need_si26 ? {{ 4{i26[25]}}, i26[25:0], 2'b0} :
                             {{14{i16[15]}}, i16[15:0], 2'b0} ;
 
assign jirl_offs = {{14{i16[15]}}, i16[15:0], 2'b0};
assign src_reg_is_rd = inst_beq | inst_bne | inst_st_w;
assign src1_is_pc    = inst_jirl | inst_bl;
assign src2_is_imm   = inst_slli_w |
                       inst_srli_w |
                       inst_srai_w |
                       inst_addi_w |
                       inst_ld_w   |
                       inst_st_w   |
                       inst_lu12i_w|
                       inst_jirl   |
                       inst_bl     ;
assign res_from_mem  = inst_ld_w;
assign dst_is_r1     = inst_bl;
assign gr_we         = ~inst_st_w & ~inst_beq & ~inst_bne & ~inst_b;
assign mem_we        = inst_st_w;
assign dest          = dst_is_r1 ? 5'd1 : rd;
 
assign rf_raddr1 = rj;
assign rf_raddr2 = src_reg_is_rd ? rd :rk;
 
assign {rf_we, rf_waddr, rf_wdata} = WB_rf_bus;
 
regfile u_regfile(
    .clk    (clk      ),
    .raddr1 (rf_raddr1),
    .rdata1 (rf_rdata1),
    .raddr2 (rf_raddr2),
    .rdata2 (rf_rdata2),
    .we     (rf_we    ),
    .waddr  (rf_waddr ),
    .wdata  (rf_wdata )
    );
 
assign rj_value  = rf_rdata1;
assign rkd_value = rf_rdata2;
 
assign ID_EX_bus = {
                    ID_pc,//150:119
                    alu_op,//118:107
                    src2_is_4,//106
                    src1_is_pc,//105
                    src2_is_imm,//104
                    gr_we,//103
                    mem_we,//102
                    dest,//101:97
                    imm,//96:65
                    rj_value,//64:33
                    rkd_value,//32:1
                    res_from_mem //0:0
};
assign rj_eq_rd = (rj_value == rkd_value);
assign br_taken = (   inst_beq  &&  rj_eq_rd
                   || inst_bne  && !rj_eq_rd
                   || inst_jirl
                   || inst_bl
                   || inst_b
                  ) && ID_valid;
assign br_target = (inst_beq || inst_bne || inst_bl || inst_b) ? (ID_pc + br_offs) :
                                                   /*inst_jirl*/ (rj_value + jirl_offs);
assign br_bus = {br_taken,//32
                br_target //31:0
                };
 
assign ID_ready_go    = 1'b1;
assign ID_allow_in     = !ID_valid || ID_ready_go && EX_allow_in;
assign ID_to_EX_valid = ID_valid && ID_ready_go && !delay_slot;
always @(posedge clk) begin
    if (reset) begin
        ID_valid <= 1'b0;
        delay_slot <= 1'b0;
    end
    else if (ID_allow_in) begin
        ID_valid <= IF_to_ID_valid;
    end
 
    if (IF_to_ID_valid && ID_allow_in) begin
        {ID_pc,ID_inst} <= IF_ID_bus;
         if (br_taken) begin
          delay_slot <= 1'b1;
          end else begin
            delay_slot <=1'b0;
          end
    end
    
end
 
endmodule

EX stage

module EX_stage(
	input         clk,
    input         reset,
    input  MEM_allow_in,
    input  ID_to_EX_valid,
	output EX_allow_in,
	input  [150:0]ID_EX_bus,
 	input  	inst_bl,
 	output [70:0]EX_MEM_bus,
 	output  EX_to_MEM_valid,
 	output        data_sram_en,
    output [ 3:0] data_sram_we,
    output [31:0] data_sram_addr,
    output [31:0] data_sram_wdata

	);

	reg  [31:0] EX_pc;

	reg EX_valid;
	wire EX_ready_go;
	reg  [11:0] EX_alu_op;
	reg         EX_src1_is_pc;
	reg         EX_src2_is_imm;
	reg         EX_src2_is_4;
	reg         EX_res_from_mem;
	reg         EX_gr_we;
	reg         EX_mem_we;
	reg  [4: 0] EX_dest;
	reg  [31:0] EX_rj_value;
	reg  [31:0] EX_rkd_value;
	reg  [31:0] EX_imm;
	wire [31:0] alu_result;
	reg EX_inst_bl;
	wire [31:0] alu_src1;
	wire [31:0] alu_src2;
	assign EX_ready_go    = 1'b1;
	assign EX_allow_in     = !EX_valid || EX_ready_go && MEM_allow_in;
	assign EX_to_MEM_valid =  EX_valid && EX_ready_go;
	assign EX_MEM_bus = {
						EX_pc,//70:39
						EX_gr_we,//38
						EX_dest,//37:33
						alu_result,//32:1
						EX_res_from_mem//0
	};

always @(posedge clk) begin
    if (reset) begin
        EX_valid <= 1'b0;
    end
    else if (EX_allow_in) begin
        EX_valid <= ID_to_EX_valid;
    end

    if (ID_to_EX_valid && EX_allow_in) begin
    	{EX_pc ,
    	EX_alu_op ,
    	EX_src2_is_4,
    	EX_src1_is_pc,
    	EX_src2_is_imm,
    	EX_gr_we,
    	EX_mem_we,
    	EX_dest,
    	EX_imm,
    	EX_rj_value,
    	EX_rkd_value,
    	EX_res_from_mem} <= ID_EX_bus;
    	EX_inst_bl <= inst_bl;
    end
end

alu u_alu(
    .alu_op     (EX_alu_op ),
    .alu_src1   (alu_src1  ),
    .alu_src2   (alu_src2  ),
    .alu_result (alu_result)
    );
assign alu_src1 = EX_src1_is_pc  ? EX_pc : EX_rj_value;
assign alu_src2 = EX_src2_is_imm ? EX_imm : (EX_inst_bl ? 32'd4 : EX_rkd_value);
assign data_sram_en = 1'b1;
assign data_sram_we    = EX_mem_we && EX_valid ? 4'b1111 : 4'b0000;
assign data_sram_addr  = alu_result;
assign data_sram_wdata = EX_rkd_value;

endmodule

MEM stage

module MEM_stage(
	input  clk,
    input  reset,
    input  WB_allow_in,
    output MEM_allow_in,
    input  [70:0]EX_MEM_bus,
	input  [31:0] data_sram_rdata,
	input  EX_to_MEM_valid,	
	output MEM_to_WB_valid,
	output [69:0]MEM_WB_bus
	);

reg [31:0] MEM_pc;
reg MEM_res_from_mem;
reg MEM_gr_we;
reg [4:0]MEM_dest;
reg [31:0]MEM_alu_result;
wire [31:0] MEM_final_result;
wire [31:0] MEM_result;

reg MEM_valid;
wire MEM_ready_go;
assign MEM_ready_go    = 1'b1;
assign MEM_allow_in     = !MEM_valid || MEM_ready_go && WB_allow_in;
assign MEM_to_WB_valid = MEM_valid && MEM_ready_go;
always @(posedge clk) begin
    if (reset) begin
        MEM_valid <= 1'b0;
    end
    else if (MEM_allow_in) begin
        MEM_valid <= EX_to_MEM_valid;
    end

    if (EX_to_MEM_valid && MEM_allow_in) begin
    	{MEM_pc ,
        MEM_gr_we ,
		MEM_dest,
		MEM_alu_result,
		MEM_res_from_mem } <= EX_MEM_bus;
    end
end
assign MEM_result = data_sram_rdata;
assign MEM_final_result = MEM_res_from_mem ? MEM_result : MEM_alu_result;
assign MEM_WB_bus = {
						MEM_pc,//69:38
						MEM_gr_we,//37
						MEM_dest,// 36:32
						MEM_final_result//31:0
};
endmodule

WB stage

module WB_stage(
  input  clk,
  input  reset,
  output WB_allow_in,
  input  MEM_to_WB_valid,
  input  [69:0] MEM_WB_bus,
  output [37:0] WB_rf_bus,
  output [31:0] debug_wb_pc,
  output [ 3:0] debug_wb_rf_we,
  output [ 4:0] debug_wb_rf_wnum,
  output [31:0] debug_wb_rf_wdata
  );
reg [31:0] WB_pc;
reg WB_valid;
wire WB_ready_go;
 
reg WB_gr_we;
reg [4:0]WB_dest;
reg [31:0]WB_final_result;
wire rf_we   ;
wire [4:0]rf_waddr;
wire [31:0]rf_wdata;
assign WB_ready_go = 1'b1;
assign WB_allow_in  = !WB_valid || WB_ready_go;
always @(posedge clk) begin
    if (reset) begin
        WB_valid <= 1'b0;
    end
    else if (WB_allow_in) begin
        WB_valid <= MEM_to_WB_valid;
    end
 
    if (MEM_to_WB_valid && WB_allow_in) begin
      {WB_pc,
       WB_gr_we,
       WB_dest,
       WB_final_result} <= MEM_WB_bus;
       
    end
end
 
assign rf_we    = WB_gr_we && WB_valid;
assign rf_waddr = WB_dest;
assign rf_wdata = WB_final_result;
 
assign WB_rf_bus = {rf_we,//37
                    rf_waddr,//36:32
                    rf_wdata//31:0
                    };
assign debug_wb_pc       = rf_we ? WB_pc : debug_wb_pc;
assign debug_wb_rf_we   = {4{rf_we}};
assign debug_wb_rf_wnum  = WB_valid && rf_we ? WB_dest : debug_wb_rf_wnum;
assign debug_wb_rf_wdata = WB_valid && rf_we ? WB_final_result : debug_wb_rf_wdata;
 
endmodule

mycpu top

module mycpu_top(
    input  wire        clk,
    input  wire        resetn,
    // inst sram interface
    output wire        inst_sram_en,
    output wire [ 3:0] inst_sram_we,
    output wire [31:0] inst_sram_addr,
    output wire [31:0] inst_sram_wdata,
    input  wire [31:0] inst_sram_rdata,
    // data sram interface
    output wire        data_sram_en,
    output wire [ 3:0] data_sram_we,
    output wire [31:0] data_sram_addr,
    output wire [31:0] data_sram_wdata,
    input  wire [31:0] data_sram_rdata,
    // trace debug interface
    output wire [31:0] debug_wb_pc,
    output wire [ 3:0] debug_wb_rf_we,
    output wire [ 4:0] debug_wb_rf_wnum,
    output wire [31:0] debug_wb_rf_wdata
);
reg         reset;
always @(posedge clk) reset <= ~resetn;

// allow_in
wire ID_allow_in;
wire EX_allow_in;
wire MEM_allow_in;
wire WB_allow_in;
//bus
wire [63:0]IF_ID_bus;
wire [150:0]ID_EX_bus;
wire [70:0]EX_MEM_bus;
wire [69:0]MEM_WB_bus;
wire [32:0]br_bus;
wire [37:0]WB_rf_bus;
//valid
wire IF_to_ID_valid;
wire ID_to_EX_valid;
wire EX_to_MEM_valid;
wire MEM_to_WB_valid;
//inst_bl
wire inst_bl;
IF_stage IF(
    .clk(clk),
    .reset(reset),
    .ID_allow_in(ID_allow_in),
    .br_bus(br_bus),
    .inst_sram_en(inst_sram_en),
    .inst_sram_we(inst_sran_we),
    .inst_sram_addr(inst_sram_addr),
    .inst_sram_wdata(inst_sram_wdata),
    .inst_sram_rdata(inst_sram_rdata),
    .IF_ID_bus(IF_ID_bus),
    .IF_to_ID_valid(IF_to_ID_valid)
    );
ID_stage ID(
   .clk(clk),
   .reset(reset),
   .EX_allow_in(EX_allow_in),
   .IF_to_ID_valid(IF_to_ID_valid),
   .IF_ID_bus(IF_ID_bus),
   .WB_rf_bus(WB_rf_bus),
   .ID_allow_in(ID_allow_in),
   .br_bus(br_bus),
   .ID_EX_bus(ID_EX_bus),
   .ID_to_EX_valid(ID_to_EX_valid),
   .to_EX_inst_bl(inst_bl)
    );
EX_stage EX(
    .clk(clk),
    .reset(reset),
    .MEM_allow_in(MEM_allow_in),
    .ID_to_EX_valid(ID_to_EX_valid),
    .EX_allow_in(EX_allow_in),
    .ID_EX_bus(ID_EX_bus),
    .inst_bl(inst_bl),
    .EX_MEM_bus(EX_MEM_bus),
    .EX_to_MEM_valid(EX_to_MEM_valid),
    .data_sram_en(data_sram_en),
    .data_sram_we(data_sram_we),
    .data_sram_addr(data_sram_addr),
    .data_sram_wdata(data_sram_wdata)
);
MEM_stage MEM(
    .clk(clk),
    .reset(reset),
    .WB_allow_in(WB_allow_in),
    .MEM_allow_in(MEM_allow_in),
    .EX_MEM_bus(EX_MEM_bus),
    .data_sram_rdata(data_sram_rdata),
    .EX_to_MEM_valid(EX_to_MEM_valid),    
    .MEM_to_WB_valid(MEM_to_WB_valid),
    .MEM_WB_bus(MEM_WB_bus)
    );
WB_stage WB(
    .clk(clk),
    .reset(reset),
    .WB_allow_in(WB_allow_in),
    .MEM_to_WB_valid(MEM_to_WB_valid),
    .MEM_WB_bus(MEM_WB_bus),
    .WB_rf_bus(WB_rf_bus),
    .debug_wb_pc(debug_wb_pc) ,
    .debug_wb_rf_we(debug_wb_rf_we),
    .debug_wb_rf_wnum(debug_wb_rf_wnum),
    .debug_wb_rf_wdata(debug_wb_rf_wdata)

    );
endmodule