锂电池充电芯片SY6912使用说明及实用

 

RS 2 Charging current program pin. Connect a current sense resistor from RS pin to

BAT pin. Average charging current is detected for both TC mode and CC mode.

充电电流程序引脚。从RS引脚到BAT引脚连接一个电流检测电阻。检测TC模式和CC模式的平均充电电流。

BAT  3 Battery positive pin.

电池正极引脚

NTC 4 Thermal protection pin. UTP threshold is about 75%VIN and OTP threshold is

about 30%VIN. Pull up to VIN can disable charging logic and make the IC operate

as normal buck regulator. Pull down to ground can shutdown the IC.

热保护针。UTP阈值约为75%VIN, OTP阈值约为NTC 4的30%VIN。上拉到VIN可以禁用充电逻辑，使IC作为正常降压稳压器工作。下拉到地面可以关闭IC。

CEL  5 Pull down for single-cell, pull high for 2 cells, open for 3 cells.

单孔向下拉，2孔向上拉，3孔打开。

STAT 6 Charging status indication pin. It is open drain output pin and can be used to turn on

a LED to indicate the charging in process. When the charging is done, LED is off.

充电状态指示引脚。它是开漏输出引脚，可以用来打开一个LED来指示充电过程。充电完成后，LED灯熄灭。

LX 7  Switch node pin. This pin connects the drains of the integrated main and

synchronous power MOSFET switches. Conn ct to external inductor.

交换节点引脚。该引脚连接集成主电源和同步功率MOSFET开关的漏极。连接到外部电感器

IN 8  Positive power supply input pin. VIN ranges f om 4V to 23V for normal operation.

It has UVLO function and must be 120mV greater than the battery voltage to

enable normal operation

电源输入正引脚。正常工作的VIN范围从4V到23V。

具有UVLO功能，必须大于电池电压120mV才能正常工作

TIM 1 Charging time limit pin. Connect this pin with a capacitor to ground. Internal  

current source charges the capacitor for TC mode and CC mode’s charging time

limit. TC charging time limit is about 1/9 of CC charging time.

充电时间限制引脚。将这个引脚与电容连接到地。内部电流源充电电容为TC模式和CC模式的充电时间限制。TC充电时间限制约为CC充电时间的1/9。

GND

Exposed pad   裸焊盘

Ground pin.  地脚电流 /以及地脚电流

Layout Design:

The layout design of SY6912A regulator is relatively

simple. For the best efficiency and minimum noise

problems, we should place the following components

close to the IC: CIN, L.

布局设计:SY6912A稳压器的布局设计比较简单。为了获得最佳效率和最小噪声问题，我们应该在IC附近放置以下组件:CIN, L。

1) It is desirable to maximize the PCB copper area

connecting to GND pin to achieve the best thermal and noise performance. If the board space allowed, aground plane is highly desirable.

1)希望最大化PCB铜的面积 连接到GND引脚，以达到最佳的热性能和噪声性能。如果电路板的空间允许， 地平面是非常理想的。

2) CIN must be close to Pins IN and GND. The loop

area formed by CIN and GND must be minimized.

Following picture is the recommended layout design of

CIN.

2) CIN必须靠近引脚IN和GND。这个循环 必须尽量减少由CIN和GND形成的面积。 下图是推荐的布局设计 CIN。

3) The PCB copper area associated with LX pin must

be minimized to avoid the potential noise problem.

1. 与LX针脚相关联的PCB铜质区域必须： 被最小化，以避免潜在的噪声问题。

4) The capacitor CTIM and the trace connecting to the

TIM pin must not be adjacent to the LX net on the PCB

layout to avoid the noise problem. It should be better to

ground CTIM to the output capacitor’s ground.

4)电容CTIM和轨迹连接到 TIM引脚不能与PCB上的LX网相邻 布局，以避免噪音问题。它应该是更好的 接地CTIM到输出电容器的接地。