设计并实现一个简单的十字路口交通灯控制电路|MOOC|Verilog|Vivado

最新推荐文章于 2024-08-10 16:19:59 发布

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最新推荐文章于 2024-08-10 16:19:59 发布

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文章标签： fpga开发课程设计

本文链接：https://blog.csdn.net/m0_74488027/article/details/139717885

版权

一、设计要求

具体要求：

以4个红色指示灯、4个绿色指示灯和4个黄色指示灯模拟路口东西南北4个方向的红绿黄交通灯。控制这些灯，使它们按照下列规律亮灭。

1、东西方向绿灯亮，南北方向红灯亮。东西方向通车，时间20秒：

2、东西方向黄灯闪烁，南北方向红灯亮，时间5秒

3、东西方向红灯亮，南北方向绿灯亮。南北方向通车，时间20秒：

4、东西方向红灯亮，南北方向黄灯闪烁，时间5秒

5、返回1，继续运行要求在仿真软件中设计并运行，或设计实际电路调试运行，提交设计报告电子档，设计报告要求包括:设计方案、电路原理图、测试参数及表格、分析结果总结，实现结果展示(要求用仿真结果截图、测试波形留或者实测照片截图及测试波形图展示实现效果）

二、实验准备

开发环境：Vivado 2017.4

编程语言：Verilog

开发板芯片：xc7a35tftg256-1

（作者的约束文件仅仅满足手上实验板要求，学校发的，但芯片是这款）

三、具体实现

3.1顶层模块

代码比较简单，不过多赘述，看注释可知含义

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 我是源神爱开源
// 
// Create Date: 2024/06/16 09:43:18
// Design Name: 
// Module Name: traffic_light
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module traffic_light(
 input clk,
 output  [7:0] data_seg,
 output  [5:0] data_dig
 
    );


reg [7:0] data_seg0;  
reg [7:0] data_seg1;  
reg [7:0] data_seg2; 
reg [7:0] data_seg3; 
reg [7:0] data_seg4; 
reg [7:0] data_seg5;

seg_scan  scan (
.clk  (clk),
.data_seg0  (data_seg0),
.data_seg1  (data_seg1),
.data_seg2  (data_seg2),
.data_seg3  (data_seg3),
.data_seg4  (data_seg4),
.data_seg5  (data_seg5),
.data_seg  (data_seg),
.data_dig  (data_dig)
);

reg [31:0] temp1 =0;
reg clk_1hz = 0;

always@(posedge clk )//分频产生1hz信号
begin
        if(temp1 < 24999999)
            begin
                clk_1hz <= 0;
                temp1 <= temp1 +1;
            end
        else if(temp1 >= 24999999&temp1< 49999999)
            begin
                clk_1hz <= 1;
                temp1 <= temp1 +1;
            end
       else if(temp1==49999999)
           begin
             temp1<=0;
            end
end

reg [5:0] cnt=0;
reg [1:0] state=0;
always@(posedge clk_1hz)//状态机
begin
         if(cnt<20)
         begin
            state<=0;
            cnt<=cnt+1;
         end
         else if(cnt<25)
          begin
            state<=1;
             cnt<=cnt+1;
          end
         else if(cnt<45)
             begin
                state<=2;
                 cnt<=cnt+1;
             end
         else if(cnt<50)
             begin
                state<=3;
                 cnt<=cnt+1;
             end 
        else if(cnt>49)
         begin
            cnt<=0;
            state<=0;
         end    
end


always@(posedge clk )//方向标识
      begin
         data_seg5 <= 8'b01011110;//东d
         data_seg4 <= 8'b01110110;//西X
         
         data_seg2 <= 8'b01010100;//南n
         data_seg1 <= 8'b01111100;//北b
      end
      

always@(posedge clk )//东西灯,红1黄2绿3
 begin
          case(state)
                3:
                begin
                      data_seg3 <= 8'b00000110;//红1
                end
                2:
                begin
                      data_seg3 <=8'b00000110 ;//红1
                end
                1://黄2闪烁
                begin
                      if(clk_1hz==1)
                      begin
                      data_seg3 <= 8'b01011011;//黄2
                      end
                      else if(clk_1hz==0)
                      begin
                      data_seg3 <= 8'b00000000;//不显示
                      end
                 end
                0:
                begin
                      data_seg3 <= 8'b01001111;//绿3
                end             
            endcase  
end

always@(posedge clk )//南北灯,红1黄2绿3
 begin
           case(state)
                0:
                begin
                      data_seg0 <= 8'b00000110;//红1
                end
                1:
                begin
                      data_seg0 <=8'b00000110 ;//红1
                end

                2:
                begin
                      data_seg0 <= 8'b01001111;//绿3
                end
                3://黄2闪烁
                begin
                      if(clk_1hz==1)
                      begin
                      data_seg0 <= 8'b01011011;//黄2
                      end
                      else if(clk_1hz==0)
                      begin
                      data_seg0 <= 8'b00000000;//不显示
                      end
                 end
             endcase              
    
end



endmodule

3.2 动态显示模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 开源使世界更伟大
// 
// Create Date: 2024/06/16 09:45:14
// Design Name: 
// Module Name: seg_scan
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//

module seg_scan(
input  clk,
input [7:0] data_seg0,
input [7:0] data_seg1,
input [7:0] data_seg2,
input [7:0] data_seg3,
input [7:0] data_seg4,
input [7:0] data_seg5,
output reg [7:0] data_seg,
output reg [5:0] data_dig
);
//分频
	reg[24:0] clk_div_cnt=0;
	reg clk_div=0;
	always @ (posedge clk)
	begin
		if (clk_div_cnt==24999)
		begin
			clk_div<=~clk_div;
			clk_div_cnt<=0;
		end
		else 
		    clk_div_cnt<=clk_div_cnt+1;
	end
	//6进制计数器
	reg [2:0] num=0;
	always @ (posedge clk_div)
	begin
		if (num>=5)
			num=0;
		else
			num=num+1;
	end

            
always@(posedge clk)
begin
       
         case(num)
           
            0:
            begin
                data_seg<=data_seg0;
                data_dig<=6'b111110;
            end
            1:
            begin
                data_seg<=data_seg1;
                data_dig<=6'b111101;
            end
          
            2:
            begin
                data_seg<=data_seg2;
                data_dig<=6'b111011;
            end
            3:
            begin
               data_seg<=data_seg3;
               data_dig<=6'b110111;
            end
            4:
            begin
               data_seg<=data_seg4;
               data_dig<=6'b101111;
            end
           5:
           begin
               data_seg<=data_seg5;
               data_dig<=6'b011111;
           end
    
         endcase
end                      
endmodule

3.3约束文件

#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets start_IBUF]
set_property IOSTANDARD LVCMOS33 [get_ports {data_dig[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_dig[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_dig[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_dig[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_dig[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_dig[5]}]
set_property PACKAGE_PIN G12 [get_ports {data_dig[0]}]
set_property PACKAGE_PIN H13 [get_ports {data_dig[1]}]
set_property PACKAGE_PIN M12 [get_ports {data_dig[2]}]
set_property PACKAGE_PIN N13 [get_ports {data_dig[3]}]
set_property PACKAGE_PIN N14 [get_ports {data_dig[4]}]
set_property PACKAGE_PIN N11 [get_ports {data_dig[5]}]
 
set_property PACKAGE_PIN T10 [get_ports {key[3]}]
set_property PACKAGE_PIN R11 [get_ports {key[2]}]
set_property PACKAGE_PIN T12 [get_ports {key[1]}]
set_property PACKAGE_PIN R12 [get_ports {key[0]}]
set_property PACKAGE_PIN T5 [get_ports {led[3]}]
set_property PACKAGE_PIN R7 [get_ports {led[2]}]
set_property PACKAGE_PIN R8 [get_ports {led[1]}]
set_property PACKAGE_PIN P9 [get_ports {led[0]}]
set_property PACKAGE_PIN R10 [get_ports {row[3]}]
set_property PACKAGE_PIN P10 [get_ports {row[2]}]
set_property PACKAGE_PIN M6 [get_ports {row[1]}]
set_property PACKAGE_PIN K3 [get_ports {row[0]}]
set_property PACKAGE_PIN D4 [get_ports clk]
#复位、启动
set_property PACKAGE_PIN F3 [get_ports rst_n]
set_property PACKAGE_PIN T9 [get_ports start]

set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports start]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {key[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {key[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {key[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {key[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {row[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {row[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {row[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {row[0]}]
set_property PACKAGE_PIN L13 [get_ports {data_seg[7]}]
set_property PACKAGE_PIN M14 [get_ports {data_seg[6]}]
set_property PACKAGE_PIN P13 [get_ports {data_seg[5]}]
set_property PACKAGE_PIN K12 [get_ports {data_seg[4]}]
set_property PACKAGE_PIN K13 [get_ports {data_seg[3]}]
set_property PACKAGE_PIN L14 [get_ports {data_seg[2]}]
set_property PACKAGE_PIN N12 [get_ports {data_seg[1]}]
set_property PACKAGE_PIN P11 [get_ports {data_seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {data_seg[0]}]
# 蜂鸣器
set_property PACKAGE_PIN L2 [get_ports buzzer]
set_property IOSTANDARD LVCMOS33 [get_ports buzzer]
# 以下为led计时灯
set_property IOSTANDARD LVCMOS33 [get_ports {state_led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {state_led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {state_led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {state_led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {state_led[4]}]

set_property PACKAGE_PIN T2 [get_ports {state_led[0]}]
set_property PACKAGE_PIN R1 [get_ports {state_led[1]}]
set_property PACKAGE_PIN G5 [get_ports {state_led[2]}]
set_property PACKAGE_PIN H3 [get_ports {state_led[3]}]
set_property PACKAGE_PIN E3 [get_ports {state_led[4]}]

四、免责声明&转载协议

该代码为本作者原创，请勿抄袭，仅仅提供参考思路，相信你可以写出比我更好的代码。

如需转载请联系作者并标明出处，感谢！

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设计并实现一个简单的十字路口交通灯控制电路|MOOC|Verilog|Vivado

具体要求：以4个红色指示灯、4个绿色指示灯和4个黄色指示灯模拟路口东西南北4个方向的红绿黄交通灯。控制这些灯，使它们按照下列规律亮灭。1、东西方向绿灯亮，南北方向红灯亮。东西方向通车，时间20秒：2、东西方向黄灯闪烁，南北方向红灯亮，时间5秒3、东西方向红灯亮，南北方向绿灯亮。南北方向通车，时间20秒：4、东西方向红灯亮，南北方向黄灯闪烁，时间5秒。
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