verilog实现32位加法器（vivado）

module addsub #(parameter WIDTH=8)
(
    input [(WIDTH-1):0] a,
    input [(WIDTH-1):0] b,
    input sub,
    output [(WIDTH-1):0] sum,
    output cf,
    output ovf,
    output sf,
    output zf
);
reg [(WIDTH-1):0] sum_reg;
reg cf_reg, ovf_reg, sf_reg, zf_reg;

always @(*) begin
    if(sub == 1'b1) begin
        sum_reg = a - b;
        cf_reg = (a < b);
    end
    else begin
        sum_reg = a + b;
        cf_reg = (sum_reg < a);
    end
    
    ovf_reg = ((a[WIDTH-1] == b[WIDTH-1]) && (sum_reg[WIDTH-1] != a[WIDTH-1]));
    sf_reg = sum_reg[WIDTH-1];
    zf_reg = (sum_reg == 0);
end
assign sum = sum_reg;
assign cf = cf_reg;
assign ovf = ovf_reg;
assign sf = sf_reg;
assign zf = zf_reg;
endmodule

仿真文件如下

`timescale 1ns / 1ps 
module addsub_sim(  ); 
// input 
reg [31:0] a = 32'd16; 
reg [31:0] b = 32'd12; 
reg sub = 0; 
//output 
wire [31:0] sum; 
wire cf; 
wire ovf; 
wire sf; 
wire zf; 
// initial 
addsub #(32) U (a,b,sub,sum,cf,ovf,sf,zf);
 initial begin 
   #200 sub = 1; 
   #200 begin a = 32'h7f; b = 32'h2; sub = 0; end 
   #200 begin a = 32'hff; b = 32'h2; sub = 0; end 
   #200 begin a = 32'h7fffffff; b = 32'h2; sub = 0; end 
   #200 begin a = 32'h16; b = 32'h17; sub = 1; end 
   #200 begin a = 32'hffff; b = 32'h1; sub = 0; end 
   #200 begin a = 32'hffffffff; b = 32'h1; sub = 0; end 
   end 
endmodule