module bjqxw(a,b,sum,cout);
input a,b;
output sum,cout;
reg sum,cout;
always @(a or b)
begin
case({a,b})
2'b00:begin
sum=0;cout=0;
end
2'b01:begin
sum=1;cout=0;
end
2'b10:begin
sum=1;cout=0;
end
2'b11:begin
sum=0;cout=1;
end
endcase
end
endmodule
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module bjqxwsimu;
reg a,b;
wire sum,cout;
bjqxw sl(a,b,sum,cout);
initial
begin
a=0;b=0;
end
always #10 {a,b}={a,b}+1;
endmodule
module qjq(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always @(a or b or cin)
begin
case ({cin,a,b})
3'b000:begin
sum=0;cout=0;
end
3'b001:begin
sum=1;cout=0;
end
3'b010:begin
sum=1;cout=0;
end
3'b011:begin
sum=0;cout=1;
end
3'b100:begin
sum=1;cout=0;
end
3'b101:begin
sum=0;cout=1;
end
3'b110:begin
sum=0;cout=1;
end
3'b111:begin
sum=1;cout=1;
end
endcase
end
endmodule
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module qjq1;
reg a,b,cin;
wire sum,cout;
qjq ul(a,b,cin,sum,cout);
initial
begin
a=0;b=0;cin=0;
end
always #10 {a,b,cin}={a,b,cin}+1;
endmodule