regfile.v

module regfile(


input wire clk,
input wire rst,

//写端口
input wire we，
input wire['RegAddrBus] waddr,
input wire['RegBus] wdata,

//读端口
input wire re1,
input wire['RegAddrBus] raddr1,
input wire['RegBus] rdata1,

//读端口2
input wire re2,
input wire['RegAddrBus] raddr2,
input wire['RegBus] rdata2,

);//端口申明完成


reg['RegBus] regs[0:'RegNum-1];

always @ (posedge clk) begin
if(rst == 'RstDisable) begin
if((we == 'WriteEnable )&&(waddr != 'RegNumLog2'h0)) begin
reg[waddr] <= wdata;
end
end
end

//读端口操作


always @ (*) begin
if(rst == 'RstEnable) begin
raddr1 <= 'ZeroWord;
end else if (raddr1 == 'RegNumLog2'h0) begin
rdata1 <= 'ZeroWord
end else if ((raddr1 == waddr) && (we == 'WriteEnable)) &&(re1 == 'ReadEnable)begin
rdata1 <= wdata;
end else if (re1 == 'ReadEnable)
rdata1 <= reg[raddr1];
end else begin
rdata1 <= 'ZeroWord；
end
end

//读端口2的操作
always @ (*) begin
if(rst == 'RstEnable) begin
raddr2 <= 'ZeroWord;
end else if (raddr2 == 'RegNumLog2'h0) begin
rdata2 <= 'ZeroWord
end else if ((raddr2 == waddr) && (we == 'WriteEnable)) &&(re2 == 'ReadEnable)begin
rdata2 <= wdata;
end else if (re2 == 'ReadEnable)
rdata2 <= reg[raddr2];
end else begin
rdata2 <= 'ZeroWord；
end

end

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