利用cpld对ads8556控制

module FSM_8556(clk_5k,clk_50,reset,convst,rd,cs,busy,rst,adc_stby,adc_range,
adc_word,adc_par, adc_hw,adc_wr);
input  clk_5k,busy,rst;
output convst,cs,rd,reset,clk_50,adc_stby,adc_range,
 adc_word,adc_par, adc_hw,adc_wr;
wire rst;
reg reset;
reg convst,cs,rd;
reg[3:0] state;
reg [15:0] busy_buffer;
reg [15:0] cnt;
reg R_clk50 = 0;
assign clk_50 =  R_clk50 ;
reg [15:0] counter = 0;
assign adc_stby   = 1;
assign adc_range  = 0;
assign adc_word   = 0;
assign adc_par    = 0;
assign adc_hw     = 0;
assign adc_wr     = 0;


parameter state0=0,state1=1,state2=2,state3=3,
state4=4,state5=5,state6=6,state7=7,
state8=8, state9=9,state10=10,state11=11,
state12=12,state13=13,state14=14,state15=15;


always@ ( posedge clk_5k )
begin
      if(counter <= 999)  // 100进制计数器
        begin
               counter <= counter  + 1;   
        end
else
        begin
               counter <= 0;
        end  
end


always@ ( posedge clk_5k )  
        begin
              if ( counter  <= 499 )
                     begin
                           R_clk50  <= 1;
end