Power Integrity

Introduction

from wiki: https://en.wikipedia.org/wiki/Power_integrity

Power Integrity

Power integrity or PI is an analysis to check whether the desired voltage and current are met from source to destination. Today, power integrity plays a major role in the success and failure of new electronic products. There are several coupled aspects of PI: on the chip, in the chip package, on the circuit board, and in the system. Four main issues must be resolved to ensure power integrity at the printed circuit board level:[1]: 615 

1. Keep the voltage ripple at the chips pads lower than the specification (e.g. less than +/-50 mV variation around 1V)
2. Control ground bounce (also called synchronous switching noise, simultaneous switching noise, or simultaneous switching output (SSN or SSO)) ==> a phenomenon where a rush of current raises the (gate) local ground voltage and "tricks" the transistors to be shut off 
3. Control electromagnetic interference and maintain electromagnetic compatibility: the power distribution network is generally the largest set of conductors on the circuit board and therefore the largest (unwanted) antenna for emission and reception of noise.
4. Maintaining a proper DC Voltage level at the load at high currents. A modern processor or field-programmable gate array can pull 1-100 Amps at sub-1V VDD levels with AC and DC margins in the tens of millivolts.[2][3] Very little DC voltage drop can thus be tolerated on the power distribution network.

Power Distribution Network (PDN)

The current path from the power supply through the PCB and IC package to the die (consumer) is called the power distribution network.[4] Its role is to transfer the power to the consumers with little DC voltage drop, and to allow little ripple induced by dynamic current at the consumer(switching current).

The DC drop occurs if there is too much resistance in the plane or power traces leading from the VRM (Voltage Regulator Module) to the consumer. This can be countered by raising the voltage on the VRM, or extending the "sense" point of the VRM to the consumer.

Dynamic current occurs when the consumer switches its transistors, typically triggered by a clock. This dynamic current can be considerably larger than the static current (internal leakage) of the consumer. This fast change in current consumption can pull the voltage of the rail down, or cause it to spike, creating a voltage ripple. This change in current happens much faster than the VRM can react. The switching current must therefore be handled by decoupling capacitors.

The noise or voltage ripple must be handled differently depending on the frequency of operation. The highest frequencies must be handled on-die. 

Target Impedance

The target impedance is the impedance at which the ripple created by the dynamic current of the specific consumer is within the specified range. The target impedance is given by the following equation[7][8] In addition to the target impedance, it is important to know which frequencies it applies, and at which frequency the consumer package is responsible (this is specified in the datasheet of the specific consumer IC).

Signal Integrity, Power Integrity and Electromagnetic Compatibility

==> or all together referred to as the Electrical Integrity of Digitial Systems

content from: 

slides by Christian Schuster, TUHH

• the issue with signal transimission:
  • Attenuation, Reflection, Dispersion, Interference, Crosstalk
• Power Delivery Issues:
  • Voltage Drop, Switching Noise, Crosstalk
• Electromagnetic Compatibility Issues:
  • Near Field Coupling, Radiated Emissions

Signal Integrity

Packaging of Digital Systems

 

Effect of Interconnect:

 see the slides for how to maintain signal integrity

Power Integrity

Effects of Power Delivery Systems

overall schematics

breakdown

IR-drop ==> loss due to resistance (of PDN)

==> there will be an extended section on IR-Drop at the end, featuring content fromTechniques to Minimize IR Drop with PI Tools

delta I-drop ==> loss due to inductance (of PDN)

PDN

schematic

 impedance in frequency domain:

 A typical maximum ripple for ditigal systems is ~5% to 10% of supply voltage, hence, 

 such a low impedance is hard to maintain for high frequencies (compute impedance for a real example and see), hence:

 Use adequate copper cross sections!

 Avoid big current loops!

 Use power/ground planes!

 Provide enough power/ground pins!

 Decouple! ==> see wiki: https://en.wikipedia.org/wiki/Decoupling_capacitor

Decoupling and How it Works

==> essentially we changed the PDN from an RL to an RLC oscillator, with better property for lower impedance in high frequency region

==> heuristic explanation:

Frequency domain: Beyond the resonance frequency the capacitor decouples the part of the PDN that lies "left" of him, i.e. the IC sees only the impedance of the capacitor.

Time domain: The capacitor stores charges close to the IC that can become currents needed for fast switching. It is like a "small battery".

==> it should be noted that since the resonance frequency is 

 it is desirable to increase damping R, and move the resonance frequency as low as needed.

==> in real world:

 and we often need multiple level of decoupling as indicated in the Intro. section:

Power/Ground Planes

Power/ground planes serve multiple purposes at the same time:

 easy access to power and ground domains for mounted components

 a "natural" decoupling capacitor for PDN improvement

 return current paths, i.e. they serve as reference conductors

 shielding between different signal layers, i.e. they reduce crosstalk

 containment for internal EM fields, i.e. reduce EM emission

BUT they show resonant behavior:

 

Summary for Adding Decoupling

==> Determine your target impedance!

 Determine your operating frequency range!

 Provide decoupling at all levels/frequencies!

 Use parallel decoupling to reduce ESR/ESL!

 Be wary of resonances! !

Minimize IR-Drop in PI

content from: 

Techniques to Minimize IR Drop with PI Tools

Key Takeaways

• The IR drop in PDNs is the main threat for achieving PI. It is important for PCB teams to carry out IR drop analysis to minimize IR drop and achieve PI in the PCB. 

• There are many interdependent factors that can impact IR drop including single or double-sided PCBs, signal flow path, trace geometry, thermal effect, impedance matching, and count and size of vias. 

• PCB simulation tools make conducting IR drop analysis much easier. ==> it's plain truth, but also know that the article is by Cadance

Factors Controlling IR Drop in PCB Planes

Manually calculating the IR drop will test your analytical and mathematical skills, and require many sheets of paper. Luckily, the advancing technology of PCB simulation tools makes manual calculations unnecessary. 

There are many interdependent factors that can impact IR drop, including the following: 

• Single-sided or double-sided PCBs—Calculating critical IR drop areas in double-sided PCBs takes much longer than calculations for single-sided PCBs.  Make sure to be cautious of trace coupling centers in multi-layered PCBs.

• Signal flow path—Just follow the signal flow path with the shortest interconnections in your layout design—half your IR drop reduction job is done.

• Trace geometry—When designing, give significant importance to the length, width, thickness, and weight of the copper trace in PDNs, as it affects the trace resistance.

• Thermal effect—IR drop generates heat, and the positive temperature coefficient of trace resistance induces a chain reaction. Your design should formulate a solution to ameliorate this cyclic process.

• Impedance matching between the different traces of different layers—As your PDN design focuses on impedance matching, you are transferring maximum power with minimum IR drop.

• Count and size of vias—The design considerations for via (through via or radial via) in your board layout can help with IR drop reduction.

Different Approaches in PCB Modeling

Modeling is the backbone of any PCB simulation software. How can you come up with an analog layout with minimum loss (minimum IR drop) PDNs using these simulations tools? Simply model the circuit with less approximation for the simulation, and re-work the layout with IR drop simulation results. As manual modeling is cumbersome, simulation tools approach modeling in two different ways: 

1. The collaboration with component companies helps to maintain well-updated databases from which the user can choose the respective component model. In this approach, parametric modeling, coding, hardware description languages, look-up tables, macro modeling form the fundamentals.

2. Encouraging custom-made models or custom-modification of primitive models in the component library. In this approach, you can create a model that is uniquely yours. This modeling approach is decided by the complexity, component technology, application and accuracy expected in the PDNs of the layout.