原来模块内容如下:
module descramble
(
input clock,
input enable,
input reset,
input in_bit,
input input_strobe,
output reg out_bit,
output reg output_strobe
);
reg [6:0] state;
reg [4:0] bit_count;
reg inited;
wire feedback = state[6] ^ state[3];
always @(posedge clock) begin
if (reset) begin
bit_count <= 0;
state <= 0;
inited <= 0;
out_bit <= 0;
output_strobe <= 0;
end else if (enable & input_strobe) begin
if (!inited) begin
state[6-bit_count] <= in_bit;
if (bit_count == 6) begin
bit_count <= 0;
inited <= 1;
end else begin
bit_count <= bit_count + 1;
end
end else begin
out_bit <= feedback ^ in_bit;
output_strobe <= 1;
state <= {state[5:0], feedback};
end
end else begin
output_strobe <= 0;
end
end
endmodule
为了学习和分析,我们按照 每个寄存器根据周围寄存器以及输入决定自己下一状态数值的思路来从新等价替换一下代码。
module descramble
(
input clock,
input enable,
input reset,
input in_bit,
input input_strobe,
output reg out_bit,
output reg output_strobe
);
reg [6:0] state;
reg [4:0] bit_count;
reg inited;
wire feedback = state[6] ^ state[3];
always @(posedge clock) if (reset)bit_count <= 0;else if (enable&input_strobe&~inited)bit_count <=(bit_count==6)?0:bit_count + 1;
always @(posedge clock) if (reset)inited<=0; else if (bit_count==6&~inited) inited<=1;
always @(posedge clock) if (reset)output_strobe<=0; else if (enable & input_strobe ) output_strobe<=inited;else output_strobe<=0;
always @(posedge clock) if (reset)out_bit<=0; else if (enable&input_strobe&inited) out_bit <= feedback ^ in_bit ;
always @(posedge clock) if (reset)state <= 0; else case ({ enable & input_strobe ,inited } )2'b10: state[6-bit_count] <= in_bit;2'b11:state <= {state[5:0], feedback};endcase
endmodule
上述代码已经已经仿真替换通过。
我们看到在灌满了6位的寄存器组state之后,每输入一位就左移一位将新输入的位放在最右边,输出是取输入和其中两位(bit3,bit6)这三位进行亦或操作输出结果。
具体在ofdm里面实现的作用在以后对ofdm的继续学习中会渐渐清晰,但是就这个代码本身来说,实现的内容还是比较简单,我们也心里有底了。一点点渗透,慢慢就觉得openofdm很亲切和熟悉了。