12位符号数转归一化float的实现

mcupro

已于 2022-03-30 07:18:45 修改

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分类专栏： ZEDBOARD+AD9361 USRP USRP之UHD 文章标签： python tornado

于 2022-03-30 00:37:45 首次发布

本文链接：https://blog.csdn.net/mcupro/article/details/123836103

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USRP 同时被 3 个专栏收录

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ZEDBOARD+AD9361

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USRP之UHD

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AD9361输出基带的12位数，表示范围是【-2048,2047】，我们现在要转成【-1，1】范围的浮点数。最简答的实现方式就是用查表的方法。我们先用以下代码做一个表格数组：



int main (){
int i , j = 0;
float f ;
for(i=-2048;i<=2047;++i) 
{
f = (float )i/2048 ;
printf("%f," , f);j++;
if (j==16) { j=0;printf("\n");}
}	
}

从上面代码看我们也可以用如下函数实现12位符号数到【-1,1】的转换：

float s12_2_float (short s12){return (float) s12/ 2048 ;}

继续说表格的实现方式：建立数组表格如下：

float u12_float_table[] = {
-1.000000,-0.999512,-0.999023,-0.998535,-0.998047,-0.997559,-0.997070,-0.996582,-0.996094,-0.995605,-0.995117,-0.994629,-0.994141,-0.993652,-0.993164,-0.992676,
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0.968750,0.969238,0.969727,0.970215,0.970703,0.971191,0.971680,0.972168,0.972656,0.973145,0.973633,0.974121,0.974609,0.975098,0.975586,0.976074,
0.976563,0.977051,0.977539,0.978027,0.978516,0.979004,0.979492,0.979980,0.980469,0.980957,0.981445,0.981934,0.982422,0.982910,0.983398,0.983887,
0.984375,0.984863,0.985352,0.985840,0.986328,0.986816,0.987305,0.987793,0.988281,0.988770,0.989258,0.989746,0.990234,0.990723,0.991211,0.991699,
0.992188,0.992676,0.993164,0.993652,0.994141,0.994629,0.995117,0.995605,0.996094,0.996582,0.997070,0.997559,0.998047,0.998535,0.999023,0.999512
};

表格建立后实现转换的代码直接成了查表，如下：

float s12_2_float (short s12){	u12_float_table[s12 + 2048]; }

原理上能提高转化效率。

对应我们写一下float转s12的代码：

short float_2_s16 (float f){ short r ;  f *= 2048  ; r = (short) f ;  }

这个无法用查表方法。


int float_2_u8 (float *a,float *b  ,int len, unsigned char *out ){
short a16,b16;
int i ;
for(i=0;i<len ;++i){
	a16 = a[i] * 2048 ;
	b16 = b[i] * 2048 ;
	out[3*i+0] = (unsigned char )a16; 
	out[3*i+1] = (unsigned char )(a16 >>8) <<4 | a17>>8 ; 
	out[3*i+2] = (unsigned char )a17;
}
}

int u24_to_u16(unsigned char *in ,int byte_len ,	short *out ){
int r,j,i = 0 ;
unsigned short t1,t2;
for (j=0,i = 0 ;i < byte_len ;i+=3){
t1 = in[i] << 4  | (in[1+i] >>4)  ;
t2 =  (in[1+i] & 0x0f) << 8  | in[2+i]  ;
if (t1 & 1<<11 ) t1 |= 0xf000 ;
if (t2 & 1<<11 ) t2 |= 0xf000 ;
out[j++] = t1 ;
out[j++] = t2 ;
}
return j;
}


int u24_to_u16x2(unsigned char *in ,int byte_len ,	short *a, short *b){
int r,j,i = 0 ;
 short  t1,t2;
for (j=0,i = 0 ;i < byte_len ;i+=2*3){
t1 = in[i] << 4  | (in[1+i] >>4)  ;
t2 =( (in[1+i] & 0x0f) << 8 ) | in[2+i]  ;
if (t1 & 1<<11 ) t1 |= 0xf000 ;
if (t2 & 1<<11 ) t2 |= 0xf000 ;
a[j+0] =  t1 ;
a[j+1] =  t2 ;

t1 = in[3+i] << 4  | (in[4+i] >>4)  ;
t2 = ( (in[4+i] & 0x0f) << 8 ) |  in[5+i]  ;
if (t1 & 1<<11 ) t1 |= 0xfffff000 ;
if (t2 & 1<<11 ) t2 |= 0xfffff000 ;
b[j+0] =   t1 ;
b[j+1] =  t2 ;
j+=2;
}

return j;

}

module IQ2FIFO(
input clk,rst,padding,

input en,a_valid,b_valid,
input [11:0] d0,d1,d2,d3,
output reg rd_ab_io,

input wr_full, // when first full ,it can allow at least 16 items
output reg  wr_fifo,
output reg [7:0] wr_data 
);

wire access_ok  = en & ~wr_full ;
wire a_or_b_valid = a_valid | b_valid ;
reg [7:0] b5,b4,b3,b2,b1,b0 ;
wire [7:0] b5w,b4w,b3w,b2w,b1w,b0w ;
reg[7:0] st,str; always @(posedge clk)  str <= st ;

always @(posedge clk) if (str == 10)  { b5,b4,b3, b2,b1,b0} <= (padding) ? 8'haa : { d3 , d2 , d1 , d0 };
assign   { b5w,b4w,b3w,b2w,b1w,b0w } = { d3 , d2 , d1 , d0 }; 

always @ (posedge clk) if (rst)  st<=0; else 
case (st) 0:st<=10;
10: case ({access_ok,a_valid,b_valid}) 
3'b110 :st<=20;
3'b101 :st<=30;
3'b111 :st<=40;  
endcase 

20: st<=21;  // save byte1    b5 
21: st<=10;  // save byte2    b4
// save byte3 when str ==21   b3

30: st<=31;  // save byte1    b2
31: st<=10;  // save byte2    b1
//  save byte3  when st==10 check str==31    b0

40:st<=41; // byte 1 b5 
41:st<=42; // byte 2 b4
42:st<=43; // byte 3 b3
43:st<=44; // byte 4 b2
44:st<=10; // byte 5 b1
// save byte6 when str==44  b0 

default st<=0;
endcase 

always @(*)rd_ab_io = ( st==10 & access_ok &  ( a_valid | b_valid ) ) ;
always @(posedge clk)  case (st)
20,21,30,31,40,41,42,43,44:wr_fifo <= 1;
default wr_fifo <= (str==21) ||(str==31) ||(str==44) ;endcase 

always@(posedge clk)  case (st)
20:wr_data <=b5w;
21:wr_data <=b4;

30:wr_data <=b2w;
31:wr_data <=b1;

40:wr_data <=b5w;
41:wr_data <=b4;
42:wr_data <=b3;
43:wr_data <=b2;
44:wr_data <=b1;
default case (str)21:wr_data<=b3;31,44:wr_data<=b0;endcase 
endcase 

endmodule



module FIFO2IQ(
input clk,rst,
input s_valid      ,
output reg  s_read      ,
input [7:0] s_din  ,
output reg [11:0] dac_q0,dac_q1,dac_q2,dac_q3,  
output reg dac_wr,
input dac_ready,
input en,q01_enable,q23_enable
);

reg [7:0]  st, str,strr ; 
reg [7:0] b0,b1,b2,b3,b4,b5 ;

always @* {dac_q0,dac_q1,dac_q2,dac_q3 }={b0,b1,b2,b3,b4,b5 };


always @ (posedge clk)  dac_wr <=   str==10 && ( strr!=10 || strr!=0 ); 
always @ (posedge clk) strr <= str ;
always @ (posedge clk) str <= st ; 
always @ (posedge clk) if ( rst ) st<=0; else case ( st )
0:st<=10;
10:if (en & s_valid & dac_ready)case ({q01_enable,q23_enable})2'b10 : st <= 20 ;2'b01 : st <= 30 ;2'b11 : st <= 40 ; endcase

20: st <= 21 ;
21: st <= 10 ; 

30: st <= 31 ;
31: st <= 10 ;

40: st <= 41 ;
41: st <= 42 ;
42: st <= 43 ;
43: st <= 44 ;
44: st <= 10 ;
default st <= 0 ;
endcase 

always @ (posedge clk) if ( st == 20 || st == 40)    b0 <= s_din ;
always @ (posedge clk) if ( st == 21 || st == 41)    b1 <= s_din ;
always @ (posedge clk) if ( str == 21 || st == 42)   b2 <= s_din ;
always @ (posedge clk) if ( st  == 30 || st ==43)    b3 <= s_din ;
always @ (posedge clk) if ( st  == 31 ||  st ==44 )  b4 <= s_din ;
always @ (posedge clk) if ( str == 31 || str ==44)   b5 <= s_din ;

always @(*) case (st) 
20,21,
30,31,40,41,42,43,
44 :s_read = 1;
10:s_read = en & s_valid & ( q01_enable | q23_enable);
default s_read = 0 ; 
endcase 

endmodule

mcupro

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