一个看门狗模块

module wdg (

input clk , 

input feed , 

output reg do_rst

);

 

parameter of_bit = 31 ; 

 

reg feedr;

always @(posedge clk) feedr<=feed;

wire is_feed  =  feedr != feed ;

 

reg [of_bit:0] d;

always @ (posedge clk) if(is_feed) d<=0;else if ( d[off_bit]==0) d<=d+1 ;

always @ (posedge clk) do_rst <= d[of_bit] ; 

 

endmodule