Omnivision examiner use only
2005 china career fair exam
1 logic design
1.there is a fifo design which the clock of data input is running at 100mhz,w
hile the clock of data output is running at 80mhz.the input data is a fix patt
ern .800 input clocks carry in 800 data continuously,and the other 200 clocks
carry in no data.how big the fifo should be in order to avoid data over/under_
run?please select the minimum depth below to meet the requirement.
A.160 b.200 c.800 d .1000
2.supposedly there is acombinational circuit between two registers driven by a
clock.what will you do if the delay of the combinational circuit is greater t
han the clock signal?
a.to reduce clock frequency b.to increase clock frequency
c.to make it pipelining d to make it multi_cycle
3.which of the follow circuits can generate gitch free gated_clk?