############################################################# # 1)Synchronous Reset ? Asynchronous Reset ? I am so confused! How will I ever know which to use ? #############################################################
Chapter
Notice
1
Reset
Why reset is needed 1) for application make machine/software escape from error or abnormal conditions 2) for simulation put circuit into a known state
Design Guideline 1) every flip-flop needs a reset (except some special cases such as shift-register where higher performance are required) 2) asynchronous reset is prefered
3
Synchronous Reset
Advantages 1) smaller flip-flops but increased combinational logic gates, even the area is smaller, the impact is not significant for today's die size. 2) may filter some glitch that is not near active clock edge
Disadvantages 1) need a pulse stretcher to garantee reset pulse width 2) need a clock , it can be an annoyance is some designs
4
Asynchronous Reset
Advantages 1) data path is clean no logic gates for reset existes in data path so higher performance can be achieved 2) circuit can be reseted with or without clock
Disadvantages 1) asynchronous de-assert leads to metastability 2) glitch or noise
5
Asynchronous Reset Problems
Reset Release, reset must be released synchronously so 1) recovery/removal timing is meeted 2) all registers exits reset state at the same time
6
Reset Synchronizer
Reset Synchronizer must be used !!! ...
7
Reset Distibution Tree
timing requirement for sync or async reset is common (setup/hold or recovery/removal), so 1) delay is required
but is diffent from clock tree 2) skew is not required
8
Reset-glitch filtering
solution Schmidt PAD Delay and then OR (not needed for all chips)
############################################################## 1)Synchronous Reset ? Asynchronous Reset ? I am so confused! How will I ever know which to use ?#######################################...