RTL Coding 读书笔记3： Finite State Machine

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# 1) The Fundamentals of Efficient Synthesizable Finite State Machine Design using NC-Verilog and BuildGates
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Style	Usage	Reason
one always block	dont use	1) more verbose 2) output assignments are more error prone to coding mistakes 3) cannot code asynchronous Mealy outputs without making the output  assignments with separate continuous assign statements.
two always block	to code FSM designs with combinational outputs	1) efficient 2) easy to code 3) easily handle Mealy FSM designs
three always block	to code FSM designs with registered outputs Note, another recommended coding style for FSM designs with registered outputs is the"output encoded" FSM coding style	1) efficient 2) easy to code

 

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# 2) Coding And Scripting Techniques For FSM Designs With Synthesis-Optimized, Glitch-Free Outputs
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Reason for register the output of FSM   1) for better timing synthesis result of multi-module design   2) output is glitch-free Method   1)  Three Always Block FSM   2)  Output Encoded FSM         it is an efficient technique for coding FSMs to drive registered outputs directly from the state register bits.         Detailed design step is discussed in this paper.

 

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# 3) Synthesizable Finite State Machine Design Techniques Using the New SystemVerilog 3.0 Enhancements
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1.0 Introduction	1.1 FSM Coding Goals   easily modifiable   easy to code and understand   compact   facilitate debugging   efficient synthesis results 1.2 Important coding style notes:   1. Make each FSM design a separate Verilog module   2. Use parameters to define state encodings instead of the Verilog `define macro   3. make state and next (next state) declarations right after the parameter assignments.   4. Code all sequential always block using nonblocking assignments   5. Code all combinational always block using blocking assignments
2.0 Review of standard Verilog FSM coding styles	2.1. Two always block style with combinational outputs (Good Style)      X's help to debug the design during simulation      X's help to optimize the design during synthesis 2.2. One sequential always block style with registered outputs - (Avoid this style!) 2.3 Three always block style with registered outputs (Good style) 2.4 Onehot coding styles     Index-parameter style with registered outputs (Good style)     Encoded-parameter style with registered outputs (Avoid this style!) 2.5 Output encoded style with registered outputs (Good style)
3.0 fsm7 Example	one always blocks style (Avoid this style!) three always blocks style (Good style)
4.0 fsm8 Example	one always blocks style (Avoid this style!) three always blocks style (Good style)
5.0 prep4 Example	one always blocks style (Avoid this style!) three always blocks style (Good style)
6.0 Coding benchmarks for standard FSM coding styles	best:   output encoded style worst:  one always block style
7.0 Synthesis benchmarks for standard FSM coding styles	Timing & Area
8.0 DC-Ultra 2002.05 FSM Tool
9.0 Verliog-2001 Enhanced Coding Styles
10.0 SystemVerilog enhancements
11.0 Implicit port connections
12.0 FSM coding with SystemVerilog 3.0	x = all X's, 'z = all Z's and '1 = all 1's
13.0 Ask your vendor to support SystemVerilog, NOW!
14.0 Conclusions	Guideline: do not use the one always block FSM coding style. Guideline: do not use state-encoded parameters to code a onehot FSM design. Use the index-encoded parameter style to implement an efficient onehot FSM design.
15.0 fsm7 Verilog & SystemVerilog code	RTL Code Example of different styles
16.0 fsm8 Verilog & SystemVerilog code	RTL Code Example of different styles
17.0 prep4 Verilog & SystemVerilog code	RTL Code Example of different styles