clock tree and skew

Clock Trees and Skew Groups
Clock trees and skew groups are the two key object types used in the CCOpt clock specification. The term object is used here
because clock tree and skew group objects can be defined, modified, and deleted using commands. For example,
create_ccopt_clock_tree , create_ccopt_skew_group , modify_ccopt_skew_group , and delete_ccopt_skew_groups .
Properties can be set per skew group or clock tree instead of globally.
For example,
set_ccopt_property
–skew_group name
target_skew value .
The report_ccopt_clock_trees and report_ccopt_skew_groups commands can be used to generate reports on clock trees and
skew groups. For more information, see the Reporting section.
Clock Trees
The union of all clock trees specifies the subset of the circuit graph that CTS will buffer. The circuit subset covered by clock tree
definitions is best referred to as a clock tree graph since clock trees may interact, for example via clock logic cells. The clock
tree graph is a single physical graph even in a multi-mode timing environment.
Maximum transition times, route types and other physical properties are associated with the clock tree graph or with individual
trees in the clock tree graph.
In all but rare exceptional circumstances, the clock tree definitions created by create_ccopt_clock_tree_spec do not require
user modification.
Skew Groups
A skew group represents a balancing constraint and is the CTS equivalent of an SDC clock. The automatically generated clock
tree specification will create one skew group per SDC clock per mode.
Each skew group has one or more sources and a number of sinks. Among other properties, a skew target and insertion delay
target can be set per skew group. Any pin in the clock tree graph can be a skew group source or sink and pins can be
designated a skew group specific ignore pin such that the specific skew group does not propagate beyond the pin.
CCOpt-CTS global skew balancing aims to achieve an equal delay, subject to the skew target, from all sources to all sinks
within each skew group. CCOpt virtually balances skew groups to zero skew to determine initial clock tree timing with
propagated clocks before optimization starts.
A skew group can be viewed as a subset of the clock tree graph superimposed on top of the clock tree graph. Skew groups can
overlap, share sources, and/or sinks.
In complex cases or with CCOpt-CTS where the SDC timing constraints do not fully capture the balancing requirements, user
adjustment to the skew group configuration may be required and/or additional skew groups can be defined.
Network Latencies
The create_ccopt_clock_tree_spec command will translate clock network latency settings to an insertion delay target on the
corresponding skew group. For example, consider the functional mode SDC constraint, “set_clock_latency 1.456 [get_clocks
{ck1}]”. The automatically generated specification will contain the following line:
set_ccopt_property target_insertion_delay -skew_group ck1/func 1.456
Similarly, pin network latency settings are translated to the insertion_delay property of a pin. This property is often referred to as a
pin insertion delay. A pin insertion delay represents the delay ‘underneath’ a clock sink. For example, for a macro clock input pin, the
pin insertion delay would represent the internal clock path delay inside the macro. Continuing the above example, add the constraint
“ set_clock_latency 0.234 [get_pins {mem1/CK}] ”. The automatically generated specification will additionally contain the
following line:
set_ccopt_property
insertion_delay
–pin mem1/CK 1.222
The prop