七位频率计vhdl

频率探测：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL IS  PORT (CLKK:IN STD_LOGIC;   CNT_EN:OUT STD_LOGIC;   RST_CNT:OUT STD_LOGIC;   load:OUT STD_LOGIC );  END FTCTRL; ARCHITECTURE behav OF FTCTRL IS  SIGNAL Div2CLK:STD_LOGIC; BEGIN  PROCESS(CLKK)  BEGIN   IF CLKK'EVENT AND CLKK = '1' THEN    Div2CLK <= NOT Div2CLK;   END IF;  END PROCESS;  PROCESS(CLKK,Div2CLK)  BEGIN   IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1';   ELSE RST_CNT <= '0'; END IF;  END PROCESS;  load <= NOT Div2CLK; CNT_EN <= Div2CLK; END behav;

四位计数器：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER10B IS  PORT(FIN:IN STD_LOGIC;   CLR:IN STD_LOGIC;   ENABL:IN STD_LOGIC;   COUNT:OUT STD_LOGIC;   DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COUNTER10B; ARCHITECTURE behav OF COUNTER10B IS  BEGIN  PROCESS(FIN,CLR,ENABL)   VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);  BEGIN   IF CLR='1' THEN CQI:=(OTHERS=>'0');   ELSIF FIN'EVENT AND FIN='1' THEN    IF ENABL='1' THEN    IF CQI<9 THEN CQI:=CQI+1;    ELSE CQI:=(OTHERS=>'0');   END IF;   END IF;   END IF;   IF CQI=9 THEN COUNT<='1';    ELSE COUNT<='0';   END IF;   DOUT<=CQI;  END PROCESS; END behav;

28位锁存器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG28B IS  PORT(LK:IN STD_LOGIC;   DIN:IN STD_LOGIC_VECTOR(27 DOWNTO 0);   DOUT:OUT STD_LOGIC_VECTOR(27 DOWNTO 0)); END REG28B; ARCHITECTURE  behav OF REG28B IS BEGIN  PROCESS(LK,DIN)  BEGIN   IF LK'EVENT AND LK='1' THEN DOUT<=DIN;   END IF;  END PROCESS; END behav;

顶层文件： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST IS  PORT(CLK1HZ:IN STD_LOGIC;   FSIN:IN STD_LOGIC;   DOUT:OUT STD_LOGIC_VECTOR(27 DOWNTO 0);   CARRY_OUT:OUT STD_LOGIC); END FREQTEST; ARCHITECTURE struc OF FREQTEST IS COMPONENT FTCTRL  PORT(CLKK:IN STD_LOGIC;   CNT_EN:OUT STD_LOGIC;   RST_CNT:OUT STD_LOGIC;   Load:OUT STD_LOGIC); END COMPONENT; COMPONENT COUNTER10B  PORT(FIN:IN STD_LOGIC;   CLR:IN STD_LOGIC;   ENABL:IN STD_LOGIC;   DOUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);   COUNT:OUT STD_LOGIC); END COMPONENT; COMPONENT REG28B  PORT(LK:IN STD_LOGIC;   DIN:IN STD_LOGIC_VECTOR(27 DOWNTO 0);   DOUT:OUT STD_LOGIC_VECTOR(27 DOWNTO 0)); END COMPONENT;  SIGNAL TSTEN1,CLR_CNT1,Load1:STD_LOGIC;  SIGNAL COUNT1,COUNT2,COUNT3,COUNT4,COUNT5,COUNT6:STD_LOGIC;  SIGNAL DTO:STD_LOGIC_VECTOR(27 DOWNTO 0); BEGIN  U1:COUNTER10B PORT MAP(FIN=>FSIN,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO(3 DOWNTO

0),COUNT=>COUNT1);  U2:COUNTER10B PORT MAP(FIN=>COUNT1,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO(7 DOWNTO 4),COUNT=>COUNT2);  U3:COUNTER10B PORT MAP(FIN=>COUNT2,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO(11 DOWNTO 8),COUNT=>COUNT3);  U4:COUNTER10B PORT MAP(FIN=>COUNT3,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO(15 DOWNTO 12),COUNT=>COUNT4);  U5:COUNTER10B PORT MAP(FIN=>COUNT4,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO(19 DOWNTO 16),COUNT=>COUNT5);  U6:COUNTER10B PORT MAP(FIN=>COUNT5,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO(23 DOWNTO 20),COUNT=>COUNT6);  U7:COUNTER10B PORT MAP(FIN=>COUNT6,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO(27 DOWNTO 24),COUNT=>CARRY_OUT);  U8:FTCTRL PORT MAP(CLKK=>CLK1HZ,CNT_EN=>TSTEN1,RST_CNT=>CLR_CNT1,Load=>Load1);  U9:REG28B PORT MAP(LK=>Load1,DIN=>DTO,DOUT=>DOUT); END struc;