What is a Good Library!

Cell libraries determine the overall performance of the synthesized logic. A good cell library will result in fast design with smallest area, whereas a poor library will degrade the final result.

Historically, the cell libraries were schematic based. Designers would choose the appropriate cell and  connect them manually to produce a netlist for the design. When the automatic synthesis engines became prevalent, the same schematic based libraries were converted and used for synthesis. However, since the synthesis engine relies on a number of factors for optimization, this approach almost always resulted in poor performance of the synthesized logic. It is therefor imperative that the cell library be designed catered solely towards the synthesis approach.

The following guidelines outline, the specific kind of cells in the technology library desired by the synthesis engine.

• A variety of drive strengths for all cells.
• Larger varieties of drive strengths for inverters and buffers.
• Cells with balanced rise and fall delays (used for clock tree buffers and gated clocks).
• Same logical function and its inversion as separate outputs, with the same physical cell (e.g. OR gate and NOR gate, as a single cell), again a variety of drive strengths.
• Complex cells ( e.g. AOI, OAI or NAND gate with one input ivnerted etc. ),   with a variety of high drive strengths. 
• High fanin cells ( e.g. AOI with 6 inputs and one output) with a range of different drive stengths.
• Varisty of flip-flops with different drive strengths, both positive and negative-edge triggered.
• Single or Multiple outputs available for each flip-flop (e.g. Q only, or QN only, or both), each with a variety of drive strengths.
• Flops to contains different inputs for Set and Reset (e.g. Set only, Reset only, no Set or Reset, both Set and Reset).
• Variety of latches, both positive and negative-edge enabled each with different drive strengths.
• Several delay cells. These are useful when fixing the hold-time violations.

Using the above guideline will result in a library optimized to handle the synthesis algorithm. This provides DC with the means to choose from a variety of cells to implement the best possible logic for the design.

It is worthwhile to note that the usage of high fanin cells, although useful in reducing the overall cell area, may cause routing congestion, which may inadvertently cause timing degradation, and/or increase in the area of the routed design. It is therefore recommended that these cells be used with caution.

Some designers prefer to exclude  the low drive strengths for high fanin cells  from the technology library. This is again is based on the algorithm used by  the routing engine and the type of placement (timing driven etc.) used by  designers. If the router is not constrained, then it uses a method by which it  associates a weight to each net of the design while placing cells. Depending  upon the weight of the net, the cells are pulled towards the source having the  highest weight. High fanin cells have a larger weight associated to its inputs

(because of the number of inputs) compared to the weight associated with their outputs (single output). Therefore, the router will place these cells near the gates that are driving it. This will result in the high fanin cell being pulled away from the cell it is supposed to be driving, causing a long net to be driven by the high fanin cell. If the high fanin cell is not strong enough to drive this long net (large capacitance) then the result will be the computation of large cell delay for the high fanin cell, as well as the driven gate (because
of slow input transition time). By eliminating the low drive strengths of the high-fanin cells from the technology library, this problem can be prevented after layout.