Cell libraries determine the overall performance of the synthesized logic. A good cell library will result in fast design with smallest area, whereas a poor library will degrade the final result.
Historically, the cell libraries were schematic based. Designers would choose the appropriate cell and connect them manually to produce a netlist for the design. When the automatic synthesis engines became prevalent, the same schematic based libraries were converted and used for synthesis. However, since the synthesis engine relies on a number of factors for optimization, this approach almost always resulted in poor performance of the synthesized logic. It is therefor imperative that the cell library be designed catered solely towards the synthesis approach.
The following guidelines outline, the specific kind of cells in the technology library desired by the synthesis engine.
- A variety of drive strengths for all cells.
- Larger varieties of drive strengths for inverters and buffers.
- Cells with balanced rise and fall delays (used for clock tree buffers and gated clocks).
- Same logical function and its inversion as separate outputs, with the same physical cell (e.g. OR gate and NOR gate, as a single cell), again a variety of drive strengths.
- Complex cells ( e.g. AOI, OAI or NAND gate with one input ivnerted etc. ), with a variety of high drive strengths.
- High fanin cells ( e.g. AOI with 6 inputs and one output) with a range of different drive stengths.
- Varisty of flip-flops with different drive strengths, both positive and negative-edge triggered.
- Single or Multiple outputs available for each flip-flop (e.g. Q only, or QN only, or both), each with a variety of drive strengths.
- Flops to contains different inputs for Set and Reset (e.g. Set only, Reset only, no Set or Reset, both Set and Reset).
- Variety of latches, both positive and negative-edge enabled each with different drive strengths.
- Several delay cells. These are useful when fixing the hold-time violations.
of slow input transition time). By eliminating the low drive strengths of the high-fanin cells from the technology library, this problem can be prevented after layout.