Note for 20140725

The job today is focus on the Matlab learning and FPGA. And this is just a note for myself learning. Of course, if you are interested in my project and what I am learning, please leave me a message.

2:24 pm

SVM+HOG

Study the influence of each stage of the computation on performance, concluding that fine-scale gradients, fine orientation binning, relatively coarse spatial binning, and high-quality local contrast normalization in overlapping descriptor blocks are all important for good results.

7:49 pm

oh, too long time.

Classical CSD Code

Starting with the LSB substitute all the 1 sequences equal or larger than two, with 10...0S. (here S means negative 1)

27D=11011B=1110S-SD=100S0S-CSD  (ps:CSD could save much more 1s than SD code before)

Optimal CSD coding

1) Starting with the LSB  substitute all 1 sequences larger than two with 10...0S. Also substitute 1011 with 110S.

2) Starting with the MSB, substitute 10S with 011.

Here is there one question that  can we also use the CSD coding to reduce the implementation effort of a fractional constant coefficient?  The answer  is yes, but the we need to be a little careful with the ordering of the operands. In VHDL the analysis of an experssion is usually done from left to right, which means an expression like 

y=7*x/8 is implemented as y=(7*x)/8, and equivalent the expression y=x/8*7 is implemented as y=(x/8)*7.

However, the latter term unfortunately will produce a large quantization error, since the evaluation of x/8 is in fact synthesized by the tool as a right shift by three bits ,so we will lose lower three bits of our input  x in the computation that follows. Let us demonstrate this with a small HDL design example.

Frational CSD Coding 

Consider coding the fractional decimal number 0.875 = 7/8 using a fractional 4 bit binary and CSD code. The 7 can be implemented more efficiently in CSD as 7=8-1 and we want to determine the quantization error