VHDL 编写一个16位乘法器 并用matlab模拟输入输出

Matrix Multiplier Core Design

Introduction

Matrix multiplication is a mathematical operation that is required in most signal processing and image processing applications. In this project the design and implementation of 32x32 matrix multiplier has been done. The matrix multiplication core accepts two input matrices element by element, each element is 16 bit. These elements or values are stored in 2 input buffers and after input storing is finished the core starts calculating the product matrix element by element and store each element in an output buffer.

A MATLAB simulation model is created to generate two random 32x32 Matrices and calculate the product of these two matrices, the MATLAB m code exports the generated input matrices and the result into text files. The generated text files for the two random matrices are used as an input source for a VHDL test bench to verify the operation of the designed matrix multiplication core.

MATLAB simulation model

 

The MATLAB simulation file generates two random matrices M1 and M2 each matrix is files with 32x32 random values in range between 0 to 100.

M1 = randsrc(32, 32, [0:1:100]); 

M2 = randsrc(32, 32, [0:1:100]); 

 

The MATLAB file then converts each matrix to a single vector and open two text files then fill it with the values of the vector in HEX format. These two text files will be used in the VHDL test bench to test the VHDL matrix multiplication core

fileID = fopen('input_A.txt','w');

B = reshape(M1',[],1);

fprintf(fileID,'val=\r\n');

for i=1:1:1024

    fprintf(fileID,'%s',