FPGA实现OPB总线收发

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前言

OPB总线是Xilinx EDK的Microblaze软核使用总线接口，但网上相关资料比较少。笔者在做项目时偶然遇到在这里提供OPB总线读写的VHDL和Verilog代码

VHDL代码

接收

代码如下：

procedure host_read
      (
        signal clk          : in    std_logic;
        constant C_ADDR     : in    unsigned(31 downto 0);
        variable RDATA      : out   unsigned(31 downto 0);
        
        signal OPB_ABus     : out   std_logic_vector(31 downto 0);
        signal OPB_BE       : out   std_logic_vector(3 downto 0);
        signal OPB_DBus_out : in    std_logic_vector(31 downto 0);
        signal OPB_RNW      : out   std_logic; 
        signal OPB_select   : out   std_logic;
        signal OPB_XferAck  : in  std_logic
      ) 
    is
      variable data_r : std_logic_vector(31 downto 0);
    begin
      OPB_ABus    <= (others => '0');
      OPB_BE      <= (others => '0');
      OPB_DBus_in <= (others => '0');
      OPB_RNW     <= '0';
      OPB_select  <= '0';
      
      wait until rising_edge(clk);
      
      OPB_select  <= '1';
      OPB_ABus    <= std_logic_vector(C_ADDR);
      OPB_RNW     <= '1';
      OPB_BE      <= X"F";
      
      wait until rising_edge(clk);
      
      while OPB_XferAck /= '1' loop
        wait until rising_edge(clk);
      end loop;
      
      RDATA := unsigned(OPB_DBus_out);
      data_r := OPB_DBus_out;
      
      OPB_ABus    <= (others => '0');
      OPB_BE      <= (others => '0');
      OPB_DBus_in <= (others => '0');
      OPB_RNW     <= '0';
      OPB_select  <= '0';
      
      assert false
      report CR&"Host read access, address = " & HexImage(C_ADDR) & ",data read = " & HexImage(data_r) &CR
      severity note;

      
      wait until rising_edge(clk);
        
    end procedure host_read;

发送

代码如下：

    procedure host_write
      (
        signal clk         : in    std_logic;
        constant C_ADDR    : in    unsigned(31 downto 0);
        constant C_WDATA   : in    unsigned(31 downto 0);
        
        signal OPB_ABus    : out   std_logic_vector(31 downto 0);
        signal OPB_BE      : out   std_logic_vector(3 downto 0);
        signal OPB_DBus_in : out   std_logic_vector(31 downto 0);
        signal OPB_RNW     : out   std_logic; 
        signal OPB_select  : out   std_logic;
        signal OPB_XferAck : in  std_logic
      ) is
    begin
      OPB_ABus    <= (others => '0');
      OPB_BE      <= (others => '0');
      OPB_DBus_in <= (others => '0');
      OPB_RNW     <= '0';
      OPB_select  <= '0';
      
      wait until rising_edge(clk);
      
      OPB_select  <= '1';
      OPB_ABus    <= std_logic_vector(C_ADDR);
      OPB_RNW     <= '0';
      OPB_BE      <= X"F";
      OPB_DBus_in <= std_logic_vector(C_WDATA);
      
      wait until rising_edge(clk);
      
      while OPB_XferAck /= '1' loop
        wait until rising_edge(clk);
      end loop;
      
      OPB_ABus    <= (others => '0');
      OPB_BE      <= (others => '0');
      OPB_DBus_in <= (others => '0');
      OPB_RNW     <= '0';
      OPB_select  <= '0';
      
      assert false
      report CR&"Host write access, address = " & HexImage(C_ADDR) & ",data written = " & HexImage(C_WDATA) &CR
      severity note;
      
      wait until rising_edge(clk);
        
    end procedure host_write;

Verilog

接收

代码如下：

module host_read(
        input                clk              ,
        input [31:0]         C_ADDR           ,
        output[31:0]         RDATA            ,
        input en                              , 
        output reg finish,
        
                                              
        output reg[31:0]         OPB_ABus         ,
        output reg[3:0]          OPB_BE           ,
        output reg [31:0]           OPB_DBus_in,
        input  [31:0]         OPB_DBus_out     ,
        output reg              OPB_RNW          ,
        output reg              OPB_select       ,
        input                OPB_XferAck 
);
wire [31:0]   data_r;
reg [3:0]   flag;
always@(en) if(en==0) flag=4'd15;


always@(posedge en) 
begin
    flag=0;
    finish = 0;
end    

always@(posedge clk)
if(flag==0)
begin
      OPB_ABus    = 32'b0;
      OPB_BE      = 32'b0;
      OPB_DBus_in  = 32'b0;
      OPB_RNW     = 1'b0;
      OPB_select  = 1'b0;
      flag=flag+1;
end      

always@(posedge clk)
if(flag==1)
begin
      OPB_select  = 1'b1;
      OPB_ABus    = C_ADDR;
      OPB_RNW     = 1'b1;
      OPB_BE      = 4'hF;
      flag=flag+1;
end    

always@(posedge clk)
if(flag==4'd2)
begin
      while (OPB_XferAck != 1'b1) 
        flag=4'd2;
      flag=flag+1;  
end

assign RDATA = OPB_DBus_out;
assign data_r = OPB_DBus_out;

always@(posedge clk)
if(flag==4'd3)
begin
      OPB_ABus    = 32'b0;
      OPB_BE      = 32'b0;
      OPB_DBus_in  = 32'b0;
      OPB_RNW     = 1'b0;
      OPB_select  = 1'b0;
      flag=flag+1;
end

always@(posedge clk)
if(flag==4)
begin
    flag = 4'd15;
    finish = 1'b1;
end


endmodule

接收

代码如下：

module host_write(
        input clk                       ,
        input [31:0] C_ADDR   ,
        input [31:0] C_WDATA  ,
        input en,
        output reg finish,
        
        output reg [31:0]           OPB_ABus,      
        output reg [3:0]           OPB_BE,        
        output reg [31:0]           OPB_DBus_in,   
        output reg               OPB_RNW,       
        output reg                 OPB_select, 
        input                    OPB_XferAck
        
);
reg [3:0]   flag;
always@(negedge en)  flag=4'd15;



always@(posedge en) 
begin
    flag=0;
    finish = 0;
end    


always@(posedge clk)
if(flag==4'd0)
begin
      OPB_ABus  = 32'b0;
      OPB_BE    = 3'b0;
      OPB_DBus_in = 32'b0;
      OPB_RNW     = 1'b0;
      OPB_select  = 1'b0;
      flag = flag+1;
end
      
always@(posedge clk)
if(flag==4'd1)
begin
      OPB_select  = 1'b1;
      OPB_ABus    = C_ADDR;
      OPB_RNW     = 0;
      OPB_BE      = 4'hF;
      OPB_DBus_in = C_WDATA;
      flag=flag+1;
end

always@(posedge clk)
if(flag==4'd2)
begin
      while (OPB_XferAck != 1'b1) 
        flag=4'd2;
      flag=flag+1;  
end

always@(posedge clk)
if(flag==4'd3)
begin
      OPB_ABus  = 32'b0;
      OPB_BE    = 3'b0;
      OPB_DBus_in = 32'b0;
      OPB_RNW     = 1'b0;
      OPB_select  = 1'b0;
      flag = flag+1;
end
      
      
always@(posedge clk)
if(flag==4'd4)
begin
    flag = 4'd15;
    finish = 1;
end



endmodule

总结

同一硬件描述语言在不同芯片上可以会出现一些综合上的问题，希望可以为大家提供一些参考。