目录
EP配置
uboot配置
1)make CROSS_COMPILE=aarch64-himix100-linux- hi3559av100_emmc_defconfig
2) make menuconfig CROSS_COMPILE=aarch64-himix100-linux-
修改配置:
3) 合入到默认的文件
uboot代码修改
devmem 0x12200c00
0x4000 0000 (RC工作模式)
static int __arch_pcie_sys_init(void)
{
unsigned int val;
/*
* * Disable PCIE
* */
val = readl(CONF_BASE_ADDR + PCIE_SYS_CTRL7);
val &= (~(1 << PCIE_APP_LTSSM_ENBALE));
writel(val, CONF_BASE_ADDR + PCIE_SYS_CTRL7);
/*
* * Reset
* */
val = readl(PERI_CRG_BASE + PERI_CRG44);
val |= (1 << PCIE_X2_SRST_REQ);
writel(val, PERI_CRG_BASE + PERI_CRG44);
/*
* * Retreat from the reset state
* */
udelay(500);
val = readl(PERI_CRG_BASE + PERI_CRG44);
val &= ~(1 << PCIE_X2_SRST_REQ);
writel(val, PERI_CRG_BASE + PERI_CRG44);
mdelay(10);
/*
* * PCIE RC work mode
* */
#if 0 // del modify to EP
val = readl(CONF_BASE_ADDR + PCIE_SYS_CTRL0);
val &= (~(0xf << PCIE_DEVICE_TYPE));
val |= (PCIE_WM_RC << PCIE_DEVICE_TYPE);
writel(val, CONF_BASE_ADDR + PCIE_SYS_CTRL0);
#endif
/*
* * Enable clk
* */
val = readl(PERI_CRG_BASE + PERI_CRG44);
val |= ((1 << PCIE_X2_BUS_CKEN)
| (1 << PCIE_X2_SYS_CKEN)
| (1 << PCIE_X2_PIPE_CKEN)
| (1 << PCIE_X2_AUX_CKEN));
writel(val, PERI_CRG_BASE + PERI_CRG44);
mdelay(10);
/*
* * Set PCIE Support Transfer Card
* */
val = readl(PERI_CRG_BASE + PCI_CARD);
val |= (1<<3);
writel(val,PERI_CRG_BASE + PCI_CARD);
mdelay;
/*
* * Set PCIE controller class code to be PCI-PCI bridge device
* */
#if 0 //del only RC need
val = readl(CONF_BASE_ADDR + PCI_CLASS_REVISION);
val &= ~(0xffffff00);
val |= (0x60400 << 8);
writel(val, CONF_BASE_ADDR + PCI_CLASS_REVISION);
#endif
udelay(1000);
/*
* * Enable controller
* */
val = readl(CONF_BASE_ADDR + PCIE_SYS_CTRL7);
val |= (1 << PCIE_APP_LTSSM_ENBALE);
writel(val, CONF_BASE_ADDR + PCIE_SYS_CTRL7);
udelay(1000);
val = readl(CONF_BASE_ADDR + PCI_COMMAND);
val |= 7;
writel(val, CONF_BASE_ADDR + PCI_COMMAND);
return 0;
}
内核代码修改
kernel/drivers/pci/hipcie/pcie_hi3559av100.c
static int __arch_pcie_sys_init(struct pcie_info *info)
和uboot中一样的代码。
带宽配置
带宽查看
SYSSTAT
devmem 0x1202008c bit12-13位
硬件管脚配置
例如将上述两个管脚都配置为下拉,则为PCIE X2。要实际测量确认为下拉才可以。