Verilog代码之求勾股定理和arctan

最新推荐文章于 2022-09-27 15:05:05 发布
最新推荐文章于 2022-09-27 15:05:05 发布
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分类专栏： 日常学习 文章标签： Verilog 求反三角函数 Verilog 求开根号 Verilog 反三角函数代码
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本文链接：https://blog.csdn.net/qq_16069457/article/details/125548174
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io_outR=√￣(io_inX*io_inX)+(io_inY*io_inY)

io_outTheta=arctan(io_inY/io_inX)   // |io_inX|<=2^14 和|io_inY|<=2^14

module PqxCordicVm(
  input         clock,
  input         reset,
  input  [31:0] io_inX,
  input  [31:0] io_inY,
  output [31:0] io_outR,
  output [31:0] io_outTheta
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
`endif  
  reg [31:0] Xns_0;  
  reg [31:0] Xns_1;  
  reg [31:0] Xns_2;  
  reg [31:0] Xns_3;  
  reg [31:0] Xns_4;  
  reg [31:0] Xns_5;  
  reg [31:0] Xns_6;  
  reg [31:0] Xns_7;  
  reg [31:0] Xns_8;  
  reg [31:0] Xns_9;  
  reg [31:0] Yns_0;  
  reg [31:0] Yns_1;  
  reg [31:0] Yns_2;  
  reg [31:0] Yns_3;  
  reg [31:0] Yns_4;  
  reg [31:0] Yns_5;  
  reg [31:0] Yns_6;  
  reg [31:0] Yns_7;  
  reg [31:0] Yns_8;  
  reg [31:0] Zns_0;  
  reg [31:0] Zns_1;  
  reg [31:0] Zns_2;  
  reg [31:0] Zns_3;  
  reg [31:0] Zns_4;  
  reg [31:0] Zns_5;  
  reg [31:0] Zns_6;  
  reg [31:0] Zns_7;  
  reg [31:0] Zns_8;  
  reg [31:0] Zns_9;  
  wire [31:0] _Xns_0_T_3 = 32'sh0 - $signed(io_inY);  
  wire [31:0] _Xns_0_T_4 = io_inY[31] ? $signed(io_inY) : $signed(_Xns_0_T_3);  
  wire [31:0] _Xns_0_T_7 = $signed(io_inX) - $signed(_Xns_0_T_4);  
  wire [31:0] _Yns_0_T_3 = 32'sh0 - $signed(io_inX);  
  wire [31:0] _Yns_0_T_4 = io_inY[31] ? $signed(io_inX) : $signed(_Yns_0_T_3);  
  wire [31:0] _Yns_0_T_7 = $signed(io_inY) + $signed(_Yns_0_T_4);  
  wire [31:0] _Zns_0_T_3 = 32'sh0 - 32'shc910;  
  wire [30:0] _Xns_1_T = Yns_0[31:1];  
  wire [31:0] _GEN_27 = {{1{_Xns_1_T[30]}},_Xns_1_T};  
  wire [31:0] _Xns_1_T_3 = $signed(Xns_0) - $signed(_GEN_27);  
  wire [30:0] _Yns_1_T = Xns_0[31:1];  
  wire [31:0] _GEN_28 = {{1{_Yns_1_T[30]}},_Yns_1_T};  
  wire [31:0] _Yns_1_T_3 = $signed(Yns_0) + $signed(_GEN_28);  
  wire [31:0] _Zns_1_T_2 = $signed(Zns_0) - 32'sh76b2;  
  wire [31:0] _Xns_1_T_7 = $signed(Xns_0) + $signed(_GEN_27);  
  wire [31:0] _Yns_1_T_7 = $signed(Yns_0) - $signed(_GEN_28);  
  wire [31:0] _Zns_1_T_5 = $signed(Zns_0) + 32'sh76b2;  
  wire [29:0] _Xns_2_T = Yns_1[31:2];  
  wire [31:0] _GEN_31 = {{2{_Xns_2_T[29]}},_Xns_2_T};  
  wire [31:0] _Xns_2_T_3 = $signed(Xns_1) - $signed(_GEN_31);  
  wire [29:0] _Yns_2_T = Xns_1[31:2];  
  wire [31:0] _GEN_32 = {{2{_Yns_2_T[29]}},_Yns_2_T};  
  wire [31:0] _Yns_2_T_3 = $signed(Yns_1) + $signed(_GEN_32);  
  wire [31:0] _Zns_2_T_2 = $signed(Zns_1) - 32'sh3eb7;  
  wire [31:0] _Xns_2_T_7 = $signed(Xns_1) + $signed(_GEN_31);  
  wire [31:0] _Yns_2_T_7 = $signed(Yns_1) - $signed(_GEN_32);  
  wire [31:0] _Zns_2_T_5 = $signed(Zns_1) + 32'sh3eb7;  
  wire [28:0] _Xns_3_T = Yns_2[31:3];  
  wire [31:0] _GEN_35 = {{3{_Xns_3_T[28]}},_Xns_3_T};  
  wire [31:0] _Xns_3_T_3 = $signed(Xns_2) - $signed(_GEN_35);  
  wire [28:0] _Yns_3_T = Xns_2[31:3];  
  wire [31:0] _GEN_36 = {{3{_Yns_3_T[28]}},_Yns_3_T};  
  wire [31:0] _Yns_3_T_3 = $signed(Yns_2) + $signed(_GEN_36);  
  wire [31:0] _Zns_3_T_2 = $signed(Zns_2) - 32'sh1fd6;  
  wire [31:0] _Xns_3_T_7 = $signed(Xns_2) + $signed(_GEN_35);  
  wire [31:0] _Yns_3_T_7 = $signed(Yns_2) - $signed(_GEN_36);  
  wire [31:0] _Zns_3_T_5 = $signed(Zns_2) + 32'sh1fd6;  
  wire [27:0] _Xns_4_T = Yns_3[31:4];  
  wire [31:0] _GEN_39 = {{4{_Xns_4_T[27]}},_Xns_4_T};  
  wire [31:0] _Xns_4_T_3 = $signed(Xns_3) - $signed(_GEN_39);  
  wire [27:0] _Yns_4_T = Xns_3[31:4];  
  wire [31:0] _GEN_40 = {{4{_Yns_4_T[27]}},_Yns_4_T};  
  wire [31:0] _Yns_4_T_3 = $signed(Yns_3) + $signed(_GEN_40);  
  wire [31:0] _Zns_4_T_2 = $signed(Zns_3) - 32'shffb;  
  wire [31:0] _Xns_4_T_7 = $signed(Xns_3) + $signed(_GEN_39);  
  wire [31:0] _Yns_4_T_7 = $signed(Yns_3) - $signed(_GEN_40);  
  wire [31:0] _Zns_4_T_5 = $signed(Zns_3) + 32'shffb;  
  wire [26:0] _Xns_5_T = Yns_4[31:5];  
  wire [31:0] _GEN_43 = {{5{_Xns_5_T[26]}},_Xns_5_T};  
  wire [31:0] _Xns_5_T_3 = $signed(Xns_4) - $signed(_GEN_43);  
  wire [26:0] _Yns_5_T = Xns_4[31:5];  
  wire [31:0] _GEN_44 = {{5{_Yns_5_T[26]}},_Yns_5_T};  
  wire [31:0] _Yns_5_T_3 = $signed(Yns_4) + $signed(_GEN_44);  
  wire [31:0] _Zns_5_T_2 = $signed(Zns_4) - 32'sh7ff;  
  wire [31:0] _Xns_5_T_7 = $signed(Xns_4) + $signed(_GEN_43);  
  wire [31:0] _Yns_5_T_7 = $signed(Yns_4) - $signed(_GEN_44);  
  wire [31:0] _Zns_5_T_5 = $signed(Zns_4) + 32'sh7ff;  
  wire [25:0] _Xns_6_T = Yns_5[31:6];  
  wire [31:0] _GEN_47 = {{6{_Xns_6_T[25]}},_Xns_6_T};  
  wire [31:0] _Xns_6_T_3 = $signed(Xns_5) - $signed(_GEN_47);  
  wire [25:0] _Yns_6_T = Xns_5[31:6];  
  wire [31:0] _GEN_48 = {{6{_Yns_6_T[25]}},_Yns_6_T};  
  wire [31:0] _Yns_6_T_3 = $signed(Yns_5) + $signed(_GEN_48);  
  wire [31:0] _Zns_6_T_2 = $signed(Zns_5) - 32'sh400;  
  wire [31:0] _Xns_6_T_7 = $signed(Xns_5) + $signed(_GEN_47);  
  wire [31:0] _Yns_6_T_7 = $signed(Yns_5) - $signed(_GEN_48);  
  wire [31:0] _Zns_6_T_5 = $signed(Zns_5) + 32'sh400;  
  wire [24:0] _Xns_7_T = Yns_6[31:7];  
  wire [31:0] _GEN_51 = {{7{_Xns_7_T[24]}},_Xns_7_T};  
  wire [31:0] _Xns_7_T_3 = $signed(Xns_6) - $signed(_GEN_51);  
  wire [24:0] _Yns_7_T = Xns_6[31:7];  
  wire [31:0] _GEN_52 = {{7{_Yns_7_T[24]}},_Yns_7_T};  
  wire [31:0] _Yns_7_T_3 = $signed(Yns_6) + $signed(_GEN_52);  
  wire [31:0] _Zns_7_T_2 = $signed(Zns_6) - 32'sh200;  
  wire [31:0] _Xns_7_T_7 = $signed(Xns_6) + $signed(_GEN_51);  
  wire [31:0] _Yns_7_T_7 = $signed(Yns_6) - $signed(_GEN_52);  
  wire [31:0] _Zns_7_T_5 = $signed(Zns_6) + 32'sh200;  
  wire [23:0] _Xns_8_T = Yns_7[31:8];  
  wire [31:0] _GEN_55 = {{8{_Xns_8_T[23]}},_Xns_8_T};  
  wire [31:0] _Xns_8_T_3 = $signed(Xns_7) - $signed(_GEN_55);  
  wire [23:0] _Yns_8_T = Xns_7[31:8];  
  wire [31:0] _GEN_56 = {{8{_Yns_8_T[23]}},_Yns_8_T};  
  wire [31:0] _Yns_8_T_3 = $signed(Yns_7) + $signed(_GEN_56);  
  wire [31:0] _Zns_8_T_2 = $signed(Zns_7) - 32'sh100;  
  wire [31:0] _Xns_8_T_7 = $signed(Xns_7) + $signed(_GEN_55);  
  wire [31:0] _Yns_8_T_7 = $signed(Yns_7) - $signed(_GEN_56);  
  wire [31:0] _Zns_8_T_5 = $signed(Zns_7) + 32'sh100;  
  wire [22:0] _Xns_9_T = Yns_8[31:9];  
  wire [31:0] _GEN_59 = {{9{_Xns_9_T[22]}},_Xns_9_T};  
  wire [31:0] _Xns_9_T_3 = $signed(Xns_8) - $signed(_GEN_59);  
  wire [31:0] _Zns_9_T_2 = $signed(Zns_8) - 32'sh80;  
  wire [31:0] _Xns_9_T_7 = $signed(Xns_8) + $signed(_GEN_59);  
  wire [31:0] _Zns_9_T_5 = $signed(Zns_8) + 32'sh80;  
  wire [63:0] _io_outR_T = $signed(Xns_9) * 32'sh9b75;  
  wire [47:0] _GEN_63 = _io_outR_T[63:16];  
  assign io_outR = _GEN_63[31:0];  
  assign io_outTheta = Zns_9;  
  always @(posedge clock) begin
    if (reset) begin  
      Xns_0 <= 32'sh0;  
    end else begin
      Xns_0 <= _Xns_0_T_7;  
    end
    if (reset) begin  
      Xns_1 <= 32'sh0;  
    end else if (Yns_0[31]) begin  
      Xns_1 <= _Xns_1_T_3;  
    end else begin
      Xns_1 <= _Xns_1_T_7;  
    end
    if (reset) begin  
      Xns_2 <= 32'sh0;  
    end else if (Yns_1[31]) begin  
      Xns_2 <= _Xns_2_T_3;  
    end else begin
      Xns_2 <= _Xns_2_T_7;  
    end
    if (reset) begin  
      Xns_3 <= 32'sh0;  
    end else if (Yns_2[31]) begin  
      Xns_3 <= _Xns_3_T_3;  
    end else begin
      Xns_3 <= _Xns_3_T_7;  
    end
    if (reset) begin  
      Xns_4 <= 32'sh0;  
    end else if (Yns_3[31]) begin  
      Xns_4 <= _Xns_4_T_3;  
    end else begin
      Xns_4 <= _Xns_4_T_7;  
    end
    if (reset) begin  
      Xns_5 <= 32'sh0;  
    end else if (Yns_4[31]) begin  
      Xns_5 <= _Xns_5_T_3;  
    end else begin
      Xns_5 <= _Xns_5_T_7;  
    end
    if (reset) begin  
      Xns_6 <= 32'sh0;  
    end else if (Yns_5[31]) begin  
      Xns_6 <= _Xns_6_T_3;  
    end else begin
      Xns_6 <= _Xns_6_T_7;  
    end
    if (reset) begin  
      Xns_7 <= 32'sh0;  
    end else if (Yns_6[31]) begin  
      Xns_7 <= _Xns_7_T_3;  
    end else begin
      Xns_7 <= _Xns_7_T_7;  
    end
    if (reset) begin  
      Xns_8 <= 32'sh0;  
    end else if (Yns_7[31]) begin  
      Xns_8 <= _Xns_8_T_3;  
    end else begin
      Xns_8 <= _Xns_8_T_7;  
    end
    if (reset) begin  
      Xns_9 <= 32'sh0;  
    end else if (Yns_8[31]) begin  
      Xns_9 <= _Xns_9_T_3;  
    end else begin
      Xns_9 <= _Xns_9_T_7;  
    end
    if (reset) begin  
      Yns_0 <= 32'sh0;  
    end else begin
      Yns_0 <= _Yns_0_T_7;  
    end
    if (reset) begin  
      Yns_1 <= 32'sh0;  
    end else if (Yns_0[31]) begin  
      Yns_1 <= _Yns_1_T_3;  
    end else begin
      Yns_1 <= _Yns_1_T_7;  
    end
    if (reset) begin  
      Yns_2 <= 32'sh0;  
    end else if (Yns_1[31]) begin  
      Yns_2 <= _Yns_2_T_3;  
    end else begin
      Yns_2 <= _Yns_2_T_7;  
    end
    if (reset) begin  
      Yns_3 <= 32'sh0;  
    end else if (Yns_2[31]) begin  
      Yns_3 <= _Yns_3_T_3;  
    end else begin
      Yns_3 <= _Yns_3_T_7;  
    end
    if (reset) begin  
      Yns_4 <= 32'sh0;  
    end else if (Yns_3[31]) begin  
      Yns_4 <= _Yns_4_T_3;  
    end else begin
      Yns_4 <= _Yns_4_T_7;  
    end
    if (reset) begin  
      Yns_5 <= 32'sh0;  
    end else if (Yns_4[31]) begin  
      Yns_5 <= _Yns_5_T_3;  
    end else begin
      Yns_5 <= _Yns_5_T_7;  
    end
    if (reset) begin  
      Yns_6 <= 32'sh0;  
    end else if (Yns_5[31]) begin  
      Yns_6 <= _Yns_6_T_3;  
    end else begin
      Yns_6 <= _Yns_6_T_7;  
    end
    if (reset) begin  
      Yns_7 <= 32'sh0;  
    end else if (Yns_6[31]) begin  
      Yns_7 <= _Yns_7_T_3;  
    end else begin
      Yns_7 <= _Yns_7_T_7;  
    end
    if (reset) begin  
      Yns_8 <= 32'sh0;  
    end else if (Yns_7[31]) begin  
      Yns_8 <= _Yns_8_T_3;  
    end else begin
      Yns_8 <= _Yns_8_T_7;  
    end
    if (reset) begin  
      Zns_0 <= 32'sh0;  
    end else if (io_inY[31]) begin  
      Zns_0 <= _Zns_0_T_3;
    end else begin
      Zns_0 <= 32'shc910;
    end
    if (reset) begin  
      Zns_1 <= 32'sh0;  
    end else if (Yns_0[31]) begin  
      Zns_1 <= _Zns_1_T_2;  
    end else begin
      Zns_1 <= _Zns_1_T_5;  
    end
    if (reset) begin  
      Zns_2 <= 32'sh0;  
    end else if (Yns_1[31]) begin  
      Zns_2 <= _Zns_2_T_2;  
    end else begin
      Zns_2 <= _Zns_2_T_5;  
    end
    if (reset) begin  
      Zns_3 <= 32'sh0;  
    end else if (Yns_2[31]) begin  
      Zns_3 <= _Zns_3_T_2;  
    end else begin
      Zns_3 <= _Zns_3_T_5;  
    end
    if (reset) begin  
      Zns_4 <= 32'sh0;  
    end else if (Yns_3[31]) begin  
      Zns_4 <= _Zns_4_T_2;  
    end else begin
      Zns_4 <= _Zns_4_T_5;  
    end
    if (reset) begin  
      Zns_5 <= 32'sh0;  
    end else if (Yns_4[31]) begin  
      Zns_5 <= _Zns_5_T_2;  
    end else begin
      Zns_5 <= _Zns_5_T_5;  
    end
    if (reset) begin  
      Zns_6 <= 32'sh0;  
    end else if (Yns_5[31]) begin  
      Zns_6 <= _Zns_6_T_2;  
    end else begin
      Zns_6 <= _Zns_6_T_5;  
    end
    if (reset) begin  
      Zns_7 <= 32'sh0;  
    end else if (Yns_6[31]) begin  
      Zns_7 <= _Zns_7_T_2;  
    end else begin
      Zns_7 <= _Zns_7_T_5;  
    end
    if (reset) begin  
      Zns_8 <= 32'sh0;  
    end else if (Yns_7[31]) begin  
      Zns_8 <= _Zns_8_T_2;  
    end else begin
      Zns_8 <= _Zns_8_T_5;  
    end
    if (reset) begin  
      Zns_9 <= 32'sh0;  
    end else if (Yns_8[31]) begin  
      Zns_9 <= _Zns_9_T_2;  
    end else begin
      Zns_9 <= _Zns_9_T_5;  
    end
  end
 
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  Xns_0 = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  Xns_1 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  Xns_2 = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  Xns_3 = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  Xns_4 = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  Xns_5 = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  Xns_6 = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  Xns_7 = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  Xns_8 = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  Xns_9 = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  Yns_0 = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  Yns_1 = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  Yns_2 = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  Yns_3 = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  Yns_4 = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  Yns_5 = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  Yns_6 = _RAND_16[31:0];
  _RAND_17 = {1{`RANDOM}};
  Yns_7 = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  Yns_8 = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  Zns_0 = _RAND_19[31:0];
  _RAND_20 = {1{`RANDOM}};
  Zns_1 = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  Zns_2 = _RAND_21[31:0];
  _RAND_22 = {1{`RANDOM}};
  Zns_3 = _RAND_22[31:0];
  _RAND_23 = {1{`RANDOM}};
  Zns_4 = _RAND_23[31:0];
  _RAND_24 = {1{`RANDOM}};
  Zns_5 = _RAND_24[31:0];
  _RAND_25 = {1{`RANDOM}};
  Zns_6 = _RAND_25[31:0];
  _RAND_26 = {1{`RANDOM}};
  Zns_7 = _RAND_26[31:0];
  _RAND_27 = {1{`RANDOM}};
  Zns_8 = _RAND_27[31:0];
  _RAND_28 = {1{`RANDOM}};
  Zns_9 = _RAND_28[31:0];
`endif  
  `endif  
end  
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif  
endmodule

 

PanYunXing130
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