BRAM_PY改善2021-06-25

32bits,之前的代码没有连续赋值 BRAM_PY，Pynq对BRAM的操作1
改进此处，现在可以连续赋值了：

assign addrb=w_addr + w_addr + w_addr + w_addr;

附录：
完整ram_test.v如下

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/04/25 17:15:36
// Design Name: 
// Module Name: ram_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


`timescale 1ns / 1ps
//
module ram_test(
            input rst,
            input clk,
            output [31:0] addrb,
			output clkb,		          	//50MHz时钟
			output [31:0] dinb,
			input [31:0] doutb,
			output enb,
			output rstb,	             	//复位信号，低电平有效	
			output [3:0]web
		);

//-----------------------------------------------------------
reg		[10:0]  		w_addr;	   		//RAM PORTA写地址
reg		[31:0] 		w_data;	   		//RAM PORTA写数据
reg 	      		wea;	    	//RAM PORTA使能
reg		[10:0]  		r_addr;	  	 	//RAM PORTB读地址
wire	[31:0] 		r_data;			//RAM PORTB读数据

/*
//产生RAM PORTB读地址
always @(posedge clkb or negedge rstb)
begin
  if(!rstb) 
	r_addr <= 9'd0;
  else if (|w_addr)			//w_addr位或，不等于0
    r_addr <= r_addr+1'b1;
  else
	r_addr <= 9'd0;	
end
*/
//产生RAM PORTA写使能信号
always@(posedge clkb or negedge rst)
begin	
  if(!rst) 
  	  wea <= 1'b0;
  else 
  begin
      if(&w_addr) 			//w_addr的bit位全为1，共写入512个数据，写入完成
        wea <= 1'b0;                 
     else               
        wea	<= 1'b1;        //ram写使能
  end 
end 

//产生RAM PORTA写入的地址及数据
always@(posedge clkb or negedge rst)
begin	
  if(!rst) 
  begin
	  w_addr <= 11'd0;
	  w_data <= 16'd1;
  end
  else 
  begin
     if(wea) 					//ram写使能有效
	 begin        
		if (&w_addr)			//w_addr的bit位全为1，共写入512个数据，写入完成
		begin
			w_addr <= w_addr ;	//将地址和数据的值保持住，只写一次RAM
			w_data <= w_data ;
		end
		else
		begin
			w_addr <= w_addr + 1'b1;
			w_data <= w_data + 1'b1;
		end
	 end
  end 
end 

assign web={wea,wea,wea,wea};

//assign dintb = w_data;
assign addrb=w_addr + w_addr + w_addr + w_addr;
assign dinb= w_data;
assign rstb = 1'b0;
assign clkb = clk;
assign enb = wea;	
endmodule