BRAM0_第一次使用BRAM有感_参考，不太成功

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2021/03/22 17:48:01
// Design Name: 
// Module Name: ram_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module ram_test(
        input clk, //50MHz时钟
        input rst_n //复位信号，低电平有效
    );
    
 //-----------------------------------------------------------
reg [8:0] w_addr; //RAM PORTA写地址
reg [15:0] w_data; //RAM PORTA写数据
reg wea; //RAM PORTA使能
reg [8:0] r_addr; //RAM PORTB读地址
wire [15:0] r_data; //RAM PORTB读数据
//产生RAM PORTB读地址
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
        r_addr <= 9'd0;
    else if (|w_addr) //w_addr位或，不等于0
        r_addr <= r_addr+1'b1;
    else
        r_addr <= 9'd0;
    end
//产生RAM PORTA写使能信号   
always@(posedge clk or negedge rst_n)
b