Chapter 4.1, Problem 1E Solution(Computer Organization and Design)

1. Step 1 of 2

   Consider fig4.2 which shows the basic implementation of the MIPS subset, with all the functional units, necessary multiplexers, and control lines.

   As the figure suggests, the basic functional units are PC (Program Counter), Instruction Memory, Registers, ALU (Arithmetic Logic Unit) and Data Memory.

   Along with these it also has a Control unit with an input (Condition Signals) and an output (Control Signals). In order to select among several possibilities depending on the type of instructions, three Multiplexers are being used, marked by the symbol MUX.

   MUX here selects any one of two options based on the select input coming from a control unit as a control signal.

   In the MIPS subset figure fig4.2 there is shown a Control unit with output lines to all the functional units. These output lines are control signals and they control these functional blocks or units.

   Here the control signals with their control function are listed:

   • BRANCH: This control signal determines what value replaces the program counter PC, whether it’s fig4.2 or the Branch destination address for the comparison instruction.

   • ALU operation: This signal determines what arithmetic operations is specified in the instruct ions, whether it is addition, subtraction or a logical operation such as AND, OR etc.

   • MEM WRITE: This signal specifies whether the Data Memory should write the data.

   • MEM READ: Similar to that of MEM WRITE, this signal specifies whether the Data Memory should read the data.

   • REG WRITE: This signal specifies whether the register should perform a write operation.

   • Control Signal to Middle MUX: This control signal selects this multiplexer with the inputs being, output from ALU and Data Memory. The output selected by this control signal writes to the register, whether it’s the ALU output being written to the register or the data from Data Memory.

   • Control Signal to Bottom MUX: The Bottommost multiplexer determines whether the second ALU input is from the registers (for an ALU instruction or a branch) or from the offset field of the instruction (for a load or store).
2. Step 2 of 2

   Consider the Instruction:

   

   And the interpretation being

   

   Here reg stands for register and AND here represents the Logical operation AND.

   In the above instruction, it is clear that it is an ALU operation not Branch instruction hence the top multiplexer will select PC+4 as the next PC.

   Further the ALU operation signal will be an AND operation.

   Also Control signal to middle MUX will be ALU and not Data Memory because ALU operation is being done here, where the output is store in another register, not a Data is being written to a register from data memory.

   Further MEM write and MEM read signal will be false as no store and load commands are used.

   Also the control signal to Bottom MUX will select that second input is from the registers and not from the offset field of the instruction (for a load and store).

   Finally the signal for REG write is going to be true as after the AND operation the output is actually written to register Rd.

   For the instruction above the values for the control signals would be

   • Branch- 0

   • Control signal to middle MUX- ALU

   • ALU operation- (bit-by-bit) AND

   • MEM WRITE- 0

   • MEM READ- 0

   • Bottom MUX- Second input is from register

   • REG write- 1 (True)