AD7124读写驱动

编者按：

        AD7124作为ADI研发的1款超高分辨率的Σ-Δ型ADC芯片，达到了惊人的24位分辨率，性能十分变态。

虽然硬件性能强悍，但是其软件驱动却十分复杂。不仔细研读半个多月手册，别想弄明白。坑不是一般的多。

        该款芯片读多通道很鸡肋，芯片只有1个data寄存器用来存放数据。这样的话，读多通道的时候，就会很容易Miss掉其它的通道。

         下面介绍下给芯片的读取技巧：

（1）从手册看问题

If several channels are enabled, the ADC automatically sequences
through the enabled channels and performs a conversion on
each channel. When a conversion is started, DOUT/RDY goes
high and remains high until a valid conversion is available and CS
is low. As soon as the conversion is available, DOUT/RDY goes low.
The ADC then selects the next channel and begins a conversion.
The user can read the present conversion while the next conversion
is being performed. As soon as the next conversion is complete,
the data register is updated; therefore, the user has a limited
period in which to read the conversion. When the ADC has
performed a single conversion on each of the selected channels,
it returns to idle mode.

If the DATA_STATUS bit in the ADC_CONTROL register is set
to 1, the contents of the status register are output along with the
conversion each time that the data read is performed. The four
LSBs of the status register indicate the channel to which the
conversion corresponds.

    Continuous Conversion Mode
Continuous conversion is the default power-up mode. The
AD7124-4 converts continuously, and the RDY bit in the status
register goes low each time a conversion is complete. If CS is low,
the DOUT/RDY line also goes low when a conversion is complete.
To read a conversion, write to the communications register,
indicating that the next operation is a read of the data register.
When the data-word is read from the data register, DOUT/RDY
goes high. The user can read this register additional times, if
required. However, the user must ensure that the data register is
not being accessed at the completion of the next conversion;
otherwise the new conversion word is lost.
When several channels are enabled, the ADC automatically
sequences through the enabled channels, performing one
conversion on each channel. When all channels are converted,
the sequence starts again with the first channel. The channels
are converted in order from lowest enabled channel to highest
enabled channel. The data register is updated as soon as each
conversion is available. The DOUT/RDY pin pulses low each
time a conversion is available. The user can then read the
conversion while the ADC converts the next enabled channel.
If the DATA_STATUS bit in the ADC_CONTROL register is set
to 1, the contents of the status register, along with the conversion
data, are output each time the data register is read. The status
register indicates the channel to which the conversion corresponds.