UVM编译报错

1.fatal error: gnu/stubs - 32.h: no such file or directory
解决办法：该报错是因为缺少32位兼容包，网上有些方案是直接安装。更简单的方法是在编译命令中加上-full64 即可正常编译。

2.Syntax error Following verilog source has syntax error:
super.new cannot be a task in SV
解决办法：检查文件名与module名不一致，修改一致即可仿真通过

3.Error-[TMAFIC] Too many arguments to function/task call
场景一：被new对象，自身需要有new函数
uvm_registry.svh,66 “amba_vip::subenv::new(name,parent)”
The above function/task call is done with more arguments than need.
解决办法：发现amba_vip_subenv中并没有写new函数，补上new函数即可。

场景二：被new对象，自身不需要定义new函数
checker.sv,270 “function_split::new(func_split, \this)”
The above function/task call is done with more arguments than need.
解决办法：发现function_split中并没有写new函数，也不需要写new函数，修改new方式
func_split= new(); 不可以用new(“func_split”, this)

4. sequence中env 相关调用报错

Error-[NOA] Null object access
The object at difference depth 1 is begin used before it was constructed/allocated.
报错代码行实际操作是
env.amba_vipenv.axi_env.slave[id].write_byte(addr, data);

解决办法：在sequence的body函数中添加code

assert( $cast(env, uvm_top.find($sformatf("*%s", "env"))))else begin
 `uvm_fatal("[top_seq]:", "FATAL, e_vseq no, cannot find env")
end

同样的报错，是针对sequence中的task调用。原因:创建了sequence句柄，但是未实例化。解决办法:

task cpu_wd();
  cpu_sedquence cpu_seq;
  cpu_seq = cpu_sequence::type_id::create("cpu_seq"); //加上改行仿真即可通过
  cpu_seq.seq_re = 'h0; //报错信息Null object access指向该行


endtask

5. 编译cmd报错

make: *** No rule to make target 'vcs', needed by 'compile'. Stop.
makefile中原代码：
compile: vcs $(CMP_OPTIONS) $(FILE_SRC)

解决办法: vcs cmd换行写即可，如下。

compile:
	 vcs $(CMP_OPTIONS) $(FILE_SRC)

6. Null object access
   top_sequence.sv,42
   The object at dereference depth 1 is being used before it was construted/allocated.
   please make sure that the object is allocated before using it.
   报错代码是

starting_phase.raise_objection(this);

报错原因：starting_phase用来在sequence中控制验证平台的关闭，只有将此要运行的sequence作为sequencer的某动态运行phase的default_sequence时，其starting_phase才不为null。本环境手动启动了对应sequence，但是没有给starting_phase赋值。
解决办法：

方法一：
   virtual task main_phase(uvm_phase phase);
       demo_seq seq0;
       seq0 = new("seq0");
       seq0.starting_phase = phase; //手动为seq0中的starting_phase赋值
       seq0.start(env.i_agt.sqr);
    endtask
方法二：
function void testcase0::build_phase(uvm_phase phase);
    super.build_phase(phase);
    mo_seq = demo_seq::type_id::create("mo_seq");
    uvm_config_db#(demo_seq)::set(this,"*.master_sequencer.main_phase","default_sequence",mo_seq);//用default sequence启动
endfunction : build_phase
代码参考 https://blog.csdn.net/wuqing0830/article/details/128331062

7. top_sequencer/p_sequencer 使用报错

Error found while trying to resolve cross-module reference.
token 'p_sequencer'. Orignating package '$unit'. Source info: uvm_pkg::\uvm_sequence_base::start (_seq, p_sequencer.sqr_cpu, \this, (-1), 0);

报错源码：
`uvm_do_on_with(cpu_seq, p_sequencer.sqr_cpu)
该报错是因为没有指定对应的p_sequencer
解决办法：
1. 在`umv_object_utils(cpu_sequence)后添加
`uvm_declare_p_sequencer(top_vsqr) //因为sqr_cpu是top_vsqr中的component
2. `uvm_do_on_with(cpu_sequence.env.top_vsqr.sqr_cpu) //直接给全路径也可

8.cpu_seq.start(env.agt.sqr) 前的uvm_info有打印，其后的umv_info未打印，仿真hang住。同时driver也收到了激励。原因：在sequence 的body 传输激励（`uvm_do_with） 后添加了get_response(rsp);
解决办法：

1. 取消该get_response 操作。
2. 在driver中补齐set_response.

源码：
seq_item_port.get_next_item(req);
drive_one_pkt(req);
seq_item_port.item_done();
修改后：
seq_item_port.get_next_item(req);
//若有多个sequence可添加
 $cast(rsp, req.clone());//缺失sequencer会报错【SQRPUT】Driver put a null response
//rsp.set_id_info(req);//缺失上一行，该行会报错Null object access, The object at dereference 1 is being used before it was constructed/allocated. 缺失该行，会报错Driver put a response with null sequence_id
drive_one_pkt(req);
seq_item_port.item_done();
set_item_port.put_response(rsp);

缺少 get_response 会报错信息 Driver put a null response. //put_response写在driver中
使用uvm_do_on_with启动sequncer可以不使用response.使用 start启动必须要response.

9. reg adpater 实例化报错

Error- [SV-EEM-SRE]  Scope resolution error
ut/hf/env/cpu_env.sv,47
$unit, "reg_adapter::type_id::create"
    Target for scope resolutio operator does not "exist". Token 'reg_adpater' is not a class/package. Originating module "$unit".
Check that class or package exists with referred toke as the same.

错误原因：实例化的module名和原module 名一致。

错误代码：

 `reg_adpater = reg_adpater::type_id::create("reg_adpater", this);`

解决办法：

reg_adapter       reg_sqr_adapter;

reg_sqr_adpater = reg_adpater::type_id::create("reg_sqr_adpater", this);

10.include 文件时，宏定义报错

Undefined macro
token is "`uvm_object_utilis_begin"
`uvm_object_utils_begin(cpu_transaction)

原因：在include报错文件之前，加上`include “uvm_macros.svh”

11.Top结构报错

Top Module/Entity not found
  Top module/entity/config "top" is no not found in the following library list
  Liblist: WORKLIB RTL DEFUALT

解决办法：查看top.sv路径，修改为正确的路径即可

12.system verilog struct使用报错

Incompatible complex type
Type of source expression is incompatible with type of target expression.
Mismatching types cannot be used in assignments, initializations and instantiations. The type of target is 'bit[31:0]$[$]', while the type of the source is 'int$[$]'.

报错源码：
typedef struct {bit[7:0] data_type[$]; bit[39:0] data_addr[$];} data_info;
data_info cpu_ram_info;
bit [31:0] idx[$]; //int idx[$];
idx = cpu_ram_info.data_addr.find_first_index_with(item==reg_dlvq_base_addr);

修改idx申明为 int idx[$]即可。

13. 将全局变量队列多次传到一个task中， 其结果未累加。
    解决办法： task里对应的队列申明前加ref.

task(bit [31:0] a[$]);
替换成
task(ref [31:0] a[$]); 该task对a 的修改则会外部可见且累加

14. Makefile报错

Makefile:128: *** missing separator. Stop.

原因：ifeq(xxx) 中间缺少空格。
正确写法：

   ifeq (xxx)//(xxx)前面为空格
   else//else 前面无法插入tab键， 可加空格
   endif//else 前面无法插入tab键， 可加空格

15.monitor 没有采到最后一笔transaction. 检查发现axi_vip 提示

svt_axi_slave_common.svp(4009) @7050000: uvm_test_top.env.amba_vip_axienv.axi_system_env.slave[0] [send_write_resp] 
{OBJECT_NUM('d10032) PORT_ID('d0) TYPE(WRITE) COHERENT_AXCT_TYPE(WRITENOSNOOP) ID('h1) SECURE('d1) ADDR('h2eb2ce28) CACHE_TYPE('h0)} TRANSACTION END

svt_axi_slave_common.svp(3120) @7050000: uvm_test_top.env.amba_vip_axienv.axi_system_env.slave[0] [recieve_write_addr] 
{OBJECT_NUM('d10033) PORT_ID('d0) TYPE(WRITE) COHERENT_AXCT_TYPE(WRITENOSNOOP) ID('h1) SECURE('d1) ADDR('h610b71ea) CACHE_TYPE('h0)} TRANSACTION END

svt_axi_slave_common.svp(3120) @7050000: uvm_test_top.env.amba_vip_axienv.axi_system_env.slave[0] [recieve_write_addr] 
{OBJECT_NUM('d10016) PORT_ID('d3) TYPE(WRITE) COHERENT_AXCT_TYPE(WRITENOSNOOP) ID('h1) SECURE('d1) ADDR('h85cacd2420) CACHE_TYPE('h0)} TRANSACTION END

这正是我没采到的那笔waddr地址。
解决办法：在body最后添加#200ns；仿真pass。测试#100ns仿真没有过， 尽量多加点时间。

16.Null object access
报错源码

agt.mon.mon_port.connect(fifo1.analysis_export);
scb.port.connect(fifo1.blcoking_ge_export);

原因： fifo 和port未new.
解决办法：在build_phase中添加new cmd即可。

fifo1=new("fifo1", this);
port=new("port",this);

17.[SV-BMFVM] Body missing for virtual method
报错log

Error -[SV-BMFVM] Body missing for virtual method
base_test.sv, 28
$unit
    Virtual method 'hwftl_base_test::build_phase' must be implemented in non-abstract class "base_test".
   Please specify the body for the virtual method.

检查环境对应行代码，发现是申明了extern virtual function void build_phase(uvm_phase phase) 。
解决办法：如果需要重载修改build_phase，则在class外面添加 完整的build_phase。
如果不需要，注释掉extern virtual function void build_phase(uvm_phase phase)；即可编译通过。

18.Too many arguments to function/task call
报错log

 Error-[TMAFIC] Too many arguments to function/task call
checker.sv,270 “function_split::new(func_split, \this)”
The above function/task call is done with more arguments than need.

问题场景：在check中new 另一个class，想调用该class中的task/function, 因此使用
funtion_split func_split;
func_split = new(func_split, this) 来new该class.

解决办法：发现function_split中并没有写new函数（也不需要写new函数），修改new方式
func_split= new();

19. variable in high conn of inout port。
    报错原因：inout 信号不能接reg类型信号
    解决办法：将reg信号值赋给wire信号，再接到inout连线上。

20. [PH_BADJUMP] 随机报错

/uvm-1.1/base/uvm_phase.svh(1706): report [PH_BADJUMP] phase reset is neither a predecessor or successor of phase run or is non-existant, so we cannot jump to it. Phase control flow is now undefined so the simulation must terminate.

原因是reset_phase jump 相关code写错了，源码：

virtual task run_phase(run phase phase);
    wait(vif.rst_n===1'h0);
    fork
          begin
                @(posedge vif.rst_n) ;
                get_and_driver();
          end
          begin
                @(posedge vif.rst_n) ;
                phase.jump(uvm_reset_phase::get());
          end
    join
endtask

解决办法: 将第9行posedge 改成negedge 即可。

virtual task run_phase(run phase phase);
    wait(vif.rst_n===1'h0);
    fork
          begin
                @(posedge vif.rst_n) ;
                get_and_driver();
          end
          begin
                @(negedge vif.rst_n) ;//修改改行即可
                phase.jump(uvm_reset_phase::get());
          end
    join
endtask

21 环境编译报错

make[1]: vlogan: Command not found
make [1]: ***[compile] Error 127

激活环境即可解决