Fsm serialdata

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    
    parameter IDIE = 0, START = 1, RD = 2, STOP = 3,UNUSE = 4;
    reg [2:0] state,next_state;
    reg [3:0] cnt;
    reg [7:0] out;
    // 驱动方程
    always @(posedge clk) begin
        if(reset)
            state <= IDIE;
        else
            state <= next_state;
    end
    
    // 状态转移方程
    always @(*) begin
        case(state)
        	IDIE : next_state <= in ? IDIE : START;
            START: next_state <= RD;
            RD   : next_state <= (cnt == 8) ? (in ? STOP : UNUSE) : RD;  // cnt是8吗？
            STOP : next_state <= in ? IDIE : START;
            UNUSE: next_state <= in ? IDIE : UNUSE;
        endcase
    end
    
    // cnt计数以及输出方程
    always @(posedge clk) begin
        case(next_state)      // 用next_state匹配输出方程就会与输入无关 ，用state匹配还要加入输入参数
            	RD   : 
                    begin
                        out[cnt] <= in;
                        cnt <= cnt+1;  // 匹配的是下一个状态，让RD加8次
                        done <=0;                   
                    end
            	STOP : 
                    begin   // 匹配的是next_state，当前state还在D7，out的输出有一拍的延时，与代码不符合
                        cnt <= 0;
                		done <=1;
                        out_byte <= out;
                    end
                default: begin
                    	cnt <= 0;
                		done <=0;
                    	out_byte <= 0;
                end
            endcase
    end
endmodule

输出时序差一拍