example1
input [7:0] data_in;
output [31:0] data_out;
<方法一>
always @(posedge clk_in or negedge rst_n)begin
if(rst_n==1'b0)begin
wdata <= 0;
end
else begin
wdata <= {wdata[23:0],data_in};
end
end
<方法二>
always @(posedge clk_in or negedge rst_n)begin
if(rst_n==1'b0)begin
wdata <= 0;
end
else if(add_cnt0)begin
wdata[31-8*cnt0 -:8] <= data_in;
end
end