HDLbits题解之--2.Verilog Language-2.1Basics

simple wire

module top_module( input in, output out );
    assign out = in;
endmodule

Four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;
endmodule

Inverter

module top_module( 
    input in, 
    output out );
    assign out = ~in;
endmodule

AND gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a&b;
endmodul

NOR gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a|b);
endmodule

XNOR gate

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a^b);
endmodule

Declaring wires

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   );
    wire cont1,cont2,cont3;
    assign cont1 = a&b;
    assign cont2 = c&d;
    assign cont3 = cont1|cont2;
    assign out = cont3;
    assign out_n = ~cont3;    
endmodule

7458 chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	wire w1,w2,w3,w4;
    assign w1 = p2a&p2b;
    assign w2 = p2c&p2d;
    assign p2y = w1|w2;
    assign w3 = p1a&p1b&p1c;
    assign w4 = p1d&p1e&p1f;
    assign p1y =w3|w4;   
endmodule