牛客网Verilog入门篇--基础语法篇

四选一多路器

`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
    reg [1:0] mux_out_r;
    always @ (*)begin
        case(sel)
            2'd0:  mux_out_r = d3;
            2'd1:  mux_out_r = d2;
            2'd2:  mux_out_r = d1;  
            2'd3:  mux_out_r = d0;
            default: mux_out_r = 2'b0;
        endcase
    end
    assign mux_out = mux_out_r;
//*************code***********//
endmodule

异步复位的串联T触发器

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg data_r1;
    always @(posedge clk or negedge rst)begin
        if (!rst)begin
            data_r1 <= 1'b0;
         end
        else if(data)begin
            data_r1 <= ~data_r1; 
        end
        else begin
            data_r1 <= data_r1;
        end
    end
        always @(posedge clk or negedge rst)begin
            if(!rst)begin
                q <= 1'b0;
            end
            else if(data_r1)begin
                q <= ~q;
            end
            else begin
               q <= q; 
            end
            
        end

//*************code***********//
endmodule

奇偶校验

`timescale 1ns/1ns
module odd_sel(
input [31:0] bus,
input sel,
output check
);
//*************code***********//

    assign check = sel? (^bus):(~(^bus));
//*************code***********//
endmodule

移位运算与乘法

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
    reg [1:0] cnt;
    reg [7:0] d_r;
    
    always @(posedge clk or negedge rst)begin
        if(rst == 1'b0)begin
           cnt <= 'b0;
           d_r <= 'b0;
           input_grant <= 'b0;
            out <= 'b0;
        end
        else begin
           cnt <= cnt+1'b1;
            case(cnt)
                2'b00:begin
                   d_r <= d;
                    input_grant <= 1;
                    out <= d;
                end
                2'b01:begin
                   input_grant <= 0;
                    out <= (d_r<<2)-d_r;
                end
                2'b10:begin
                   input_grant <= 0;
                    out <= (d_r<<3)-d_r;
                end
                2'b11:begin
                    input_grant <= 0;
                    out <= (d_r<<3);
                end
            endcase
        end
                
    end

//*************code***********//
endmodule

拆分与运算

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
    reg [15:0]d_r;
    always @(posedge clk or negedge rst)begin
        if(rst == 1'b0)begin
           d_r <= 0; 
        end
        else if(sel == 2'b00)begin
            d_r <= d;
        end
    end
    always @(posedge clk or negedge rst)begin
        if(rst == 1'b0)begin
            out <= 'b0;
            validout <=1'b0;
        end
        else begin
            case(sel)
                2'd1:begin
                    out <= d_r[3:0]+d_r[7:4];
                    validout <= 1'b1;
                end
                2'd2:begin
                    out <= d_r[3:0]+d_r[11:8];
                    validout <= 1'b1;                    
                end
                2'd3:begin
                    out <= d_r[3:0]+d_r[15:12];
                    validout <= 1'b1;
                end
                default:begin
                    out <= 'b0;
                    validout <= 1'b0;                    
                end                                
            endcase
        end
        
    end
//*************code***********//
endmodule

多功能数据处理器

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);
    
    always @(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)begin
            c <= 9'b0;
        end
        else begin
            case(select)
                2'd0: c<=a;
                2'd1: c<=b;
                2'd2: c<=a+b;
                2'd3: c<=a-b;
                default:
                    c<='b0;
            endcase
        end   
    end   
endmodule

求两个数的差值

`timescale 1ns/1ns
module data_minus(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,

	output  reg [8:0]c
);
    always @(posedge clk or negedge rst_n)begin
        if(rst_n == 1'b0)
            c <= 9'b0;
        else if (a>b)
            c <= a-b;
        else 
            c <= b-a;
    end
        
endmodule

使用generate…for语句简化代码

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);
genvar i;
generate
    for(i=0;i<8;i=i+1)begin:gen_data_tmp
        assign data_out[i] = data_in[7-i];
    end
endgenerate 
endmodule

使用子模块实现三输入数的大小比较

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,	
	output [7:0]d
);
    wire [7:0] ab_l;
    wire [7:0] ac_l;
    compar u_compar0(
        .clk(clk),
        .rst_n(rst_n),
        .a(a),
        .b(b),
        .c(ab_l)        
    );
    compar u_compar1(
        .clk(clk),
        .rst_n(rst_n),
        .a(a),
        .b(c),
        .c(ac_l)    
    );
    compar u_compar2(
        .clk(clk),
        .rst_n(rst_n),
        .a(ab_l),
        .b(ac_l),
        .c(d)         
    );    
endmodule
   module compar(
        input clk,
        input rst_n,
        input [7:0]a,
        input [7:0]b,
        output reg [7:0] c
    );
        always @(posedge clk or negedge rst_n)begin
            if(rst_n == 1'b0)
                c <= 'b0;
            else if (a<=b)
                c <= a;
            else
                c <=b;
        end
    endmodule

使用函数实现数据大小端转换

`timescale 1ns/1ns
module function_mod(
	input [3:0]a,
	input [3:0]b,
    input clk,
    input rst_n,
	
	output [3:0]c,
	output [3:0]d
);
    assign c = rst_n?data_rvs(a):0;
    assign d = rst_n?data_rvs(b):0;
     
// --function        
        function [3:0] data_rvs;
        input [3:0] data_in;
        integer k;
        begin
            for (k=0;k<4;k=k+1) begin
                data_rvs[3-k]=data_in[k];
            end            
        end
    endfunction
endmodule