编译仿真的错误警告
包含在学习FPGA过程软件或代码出现的各种错误及警告,以及对应的处理方法。
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记录学习FPGA过程,学习中遇到的问题,学习各种接口,高速传输,也会将自己所做的留下来,敬请大家多多交流。
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quartus编译报错:Error (176310): Can‘t place multiple pins assigned to pin location Pin_F16 (IOPAD_X34_Y1
整体错误信息:Error (176310): Can't place multiple pins assigned to pin location Pin_F16 (IOPAD_X34_Y18_N21) Info (176311): Pin VGA_VS is assigned to pin location Pin_F16 (IOPAD_X34_Y18_N21) Info (176311): Pin ~ALTERA_nCEO~ is assi...转载 2020-09-28 10:10:32 · 8848 阅读 · 7 评论 -
xilinx vivado 2019 驱动问题,Connecting to hw_server url TCP:localhost:3121,jtag连接不上
问题:在对vivado2019.2软件中烧写比特流时,打开硬件目标找不到JTAG,open target连接不上,显示信息为:INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042解决方法:一般情况下是因为Vivado的驱动没有安装好,只需要将驱动安装上即可,路原创 2020-07-04 14:39:13 · 14565 阅读 · 7 评论 -
FPGA verilog 警告:复位中的陷阱
今天在写I2C接口,分析和综合代码时,出现了一个以前没见过或者很少见的警告,这里记录一下:先看代码://设备地址always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin device_addr_a <= {4'b1010,device_addr,1'b0}; end else if(wr_flag) begin device_addr_a <= {4'b1原创 2020-05-27 17:07:52 · 2194 阅读 · 6 评论 -
FPGA Verilog分析综合时警告:Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity
警告:Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder解决过程:看到这个警告,定位不到哪里出现问题,从网上找了下,定位如下:在编译报告上,选择如下图位置,便可以知道,出现在什么地方了。出现“hierarchies”这个词基...原创 2020-04-09 20:09:11 · 4180 阅读 · 0 评论 -
FPGA verilog 三态门设计及在quartus编译和Modelsim里仿真问题
三态门原创 2020-03-27 15:15:08 · 6086 阅读 · 0 评论 -
Modelsim仿真时自动优化出不来波形
在对Verilog代码用Modelsim仿真时,Modelsim自动优化出不来波形如下仿真时信息:vsim work.SDRAM_interface_tb# vsim # Start time: 14:57:38 on Mar 28,2020# ** Note: (vsim-8009) Loading existing optimized design _opt# # Load...原创 2020-03-28 15:27:45 · 4225 阅读 · 0 评论 -
FPGA Verilog编译报错:Number of processors has not been specified which may cause overloading on shared
错误信息:FPGA在写Verilog时编译报错,具体错误信息如下:Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in y...原创 2020-03-22 11:24:47 · 4962 阅读 · 1 评论 -
FPGA Verilog编译时警告Warning (10230): truncated value with size 32 to match size of target (3)
完整警告:Warning (10230): Verilog HDL assignment warning at digital_clock.v(75): truncated value with size 32 to match size of target原因:在写Verilog的计数程序时,很多人或者很多教程都是这样写:always @(posedge clk or neg...原创 2020-03-14 12:14:41 · 13934 阅读 · 3 评论 -
Verilog用Modelsim仿真时错误:Instantiating 'u_state_machine_pkt_top' has exceeded the recursion depth limit
错误信息:Instantiating 'u_state_machine_pkt_top' has exceeded the recursion depth limit of 200. (实例化“ u_state_machine_pkt_top”已超过递归深度限制200。)原因:测试文件的模块名和实例化文件模块名一样,造成嵌套死循环,递归深度无限大。如下图所示...原创 2020-03-10 20:23:41 · 4060 阅读 · 5 评论 -
FPGA Verilog分析与综合时出错:Error (10029): Constant driver at state_machine_pkt_top.v(144)
在对Verilog程序分析与综合时,发生错误信息如下:Error (10028): Can't resolve multiple constant drivers for net "data_cnt[15]" at state_machine_pkt_top.v(160)Error (10029): Constant driver at state_machine_pkt_top.v(144...原创 2020-03-10 18:07:31 · 5422 阅读 · 0 评论