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骇浪涛
北京大学徐鹏涛,可通过18329358288@163.com邮箱联系
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封装verilog代码成AXI_IP核,实现PYNQ调用
参考: https://blog.csdn.net/shushm/article/details/49536845 verilog封装IP核(sum) https://www.cnblogs.com/chengqi521/p/7987714.html verilog封装IP核(LED)(1) https://www.cnblogs.com/chengqi521/p/7988031.html verilog封装IP核(LED)(2) 约束文件添加 https://blog.csdn.net/limoon121原创 2020-08-13 23:35:39 · 2135 阅读 · 4 评论 -
Ultra 96V2 PS/PL(BRAM交互共享数据) PYNQ
环境:PYNQ、Ultra96 V2、Vivado2018.3 具体流程: 结构简图(https://blog.csdn.net/rzjmpb/article/details/50365915# ) (1) 创建Vivado工程,选择Ultra 96板; (2) Create Block Design; (3) Add ZYNQ,Run Block Automation; (4) 添加AXI_BRAM_CTRL x2(一个write、一个read), 并把number of BRAM interfa原创 2020-07-29 18:13:12 · 800 阅读 · 0 评论