Verilog语言中的运算符具有优先级顺序
- 无论在代码书写中各个符号的前后顺序如何,Verilog根据符号优先级顺序处理逻辑
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- Latex代码:
\subsection{Verilog描述符优先级}
\doublerulesep=2pt
\begin{tabular}{|c|c|}\hline
\multicolumn{2}{|c|}{Verilog描述符优先级}\\ \hline
1 & $!$ $\~{}$ \\ \hline
2 & $*$ $/$ $\%$ \\ \hline
3 & $+$ $-$ \\ \hline
4 & $<<$ $>>$ \\ \hline
5 & $<$ $<=$ $>$ $>=$ \\ \hline
6 & $==$ $!=$ $===$ $!===$ \\ \hline
7 & $\&$ \\ \hline
8 & $\^{}$ $\^{}\~{}$ \\ \hline
9 & $|$ \\ \hline
10 & $\&\&$ \\ \hline
11 & $||$ \\ \hline
12 & $?:$ \\ \hline
\end{tabular}