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Verilog 错误
# ** Error: (vlog-7) Failed to open design unit file "F:/FPGAPro/plus_counter_1/tb/plus_counter_1_tb.v" in read mode.# No such file or directory. (errno = ENOENT)# End time: 00:44:36 on Oct 25,2022, Elapsed time: 0:00:00# Errors: 1, Warnings: 0原创 2022-10-24 23:46:13 · 659 阅读 · 0 评论 -
Verilog与FPGA #1 入门:分析一个4位二进制加法计数器
数字IC与FPGA #1 入门:分析一个4位二进制加法计数器原创 2022-10-24 23:07:16 · 8144 阅读 · 5 评论