# ** Error: (vlog-7) Failed to open design unit file "F:/FPGAPro/plus_counter_1/tb/plus_counter_1_tb.v" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 00:44:36 on Oct 25,2022, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
发现setting tb文件路径刚才改过忘了改