???A Cache Simulator

Cache memories have been used widely in current microprocessor systems. In this problem, you are asked to write a program for a cache simulator. The cache has the following metrics:

1. The cache size is 1 KB (K-byte).

2. The cache uses the direct mapped approach.

3. The cache line size is 16 bytes.

4. The cacheable memory size is 256MB.

Your program will report a hit or miss when an address is given to the cache simulator. This is often called trace simulation. Initially, all of the cache lines are in the invalid state. When a memory line is first brought into the cache, the allocated cache entry transits into the valid state. Assume that a miss causes the filling of a whole cache line.

Input Format

Up to $100$ lines of address can be given in the file. Each line consists of an address given to the simulator. The address is given in hexadecimal form. We assume that each address references only one byte of data. The input file ends at the line with the word $END$.

Output Format

Report either $Hit$ or $Miss$ for each of the given addresses. The last line reports cache hit ratio in percentage, that is, the number of hits divided by the number of total addresses given.

样例输入

AAAA000
00010B2
00010BA
END

样例输出

Miss
Miss
Hit
Hit ratio = 33.33%

题目来源

2017 ACM-ICPC 亚洲区（南宁赛区）网络赛