Verilog HDL语言编写与门、与非门、或门、或非门、同或、异或、缓冲器、非门。

1、代码

module Gate(S_in1,S_in2,Out_and,Out_nand,Out_or,Out_nor,Out_xnor,Out_xor,Out_buf,Out_not);

input S_in1;
input S_in2;
output Out_and,Out_nand,Out_or,Out_nor,Out_xnor,Out_xor,Out_buf,Out_not;

 

and(Out_and,S_in1,S_in2); //与门
nand(Out_nand,S_in1,S_in2); //与非门
or(Out_or,S_in1,S_in2);//或门
nor(Out_nor,S_in1,S_in2);//或非门
xnor(Out_xnor,S_in1,S_in2);//同或
xor(Out_xor,S_in1,S_in2);//异或门
buf(Out_buf,S_in1);//缓冲器
not(Out_not,S_in1);//非门
//nand na1 3inp(Out_nand,S_in1,S_in2,S_in3)//三个输入

 

endmodule 

2、testbench

`timescale 1ns/1ns

module Gate_tb;
reg S_in1;
reg S_in2;
wire Out_and;
wire Out_nand;
wire Out_or;
wire Out_nor;
wire Out_xnor;
wire Out_xor;
wire Out_buf;
wire Out_not;

 

Gate u0(
    .S_in1(S_in1),
    .S_in2(S_in2),
    .Out_and(Out_and),
    .Out_nand(Out_nand),
    .Out_or(Out_or),
    .Out_nor(Out_nor),
    .Out_xnor(Out_xnor),
    .Out_xor(Out_xor),
    .Out_buf(Out_buf),
    .Out_not(Out_not)
);
initial begin
S_in1=0;S_in2=0;
#100;
S_in1=0;S_in2=1;
#100;
S_in1=1;S_in2=0;
#100;
S_in1=1;S_in2=1;
#100;
end
endmodule