第十天 iic协议

今天学习的iic的协议，没用别的模块连接此iic协议，只有sda表示出的数据波形。

module iic(
            clk,
            rst_n,
            key_wr,
            key_rd,
            data_in,
            scl,
            sda,
            data_out

    );
input                   clk         ;
input                   rst_n       ;
input                   key_wr      ;
input                   key_rd      ;
input       [7:0]       data_in     ;


output      reg         scl         ;
output      reg   [7:0] data_out    ;


inout                   sda         ;

reg sda_buffer;
reg flag;

assign sda = (flag) ? sda_buffer : 1'bz;

reg [7:0] count                     ;
reg       clk_sys                   ;

always @(posedge clk or negedge rst_n)
if(!rst_n)
    begin
        clk_sys <= 1'b0;
        count <= 'd0;
    end 
else
    begin
        if(count < 31)
            count <= count + 1'b1;//800khz的时钟频率
        else
            begin
            clk_sys <= ~clk_sys;
            count <= 'd0;
            end 
    end
reg [5:0] state;
always @(negedge clk_sys or negedge rst_n)
if(!rst_n)
    begin
        scl <= 1'b1;//空闲时刻
    end
else
    begin
        if(state > 'd0)
            scl <= ~scl;
        else
            scl <= 1'b1;
    end
reg [1:0] en;

always @(posedge clk or negedge rst_n)
if(!rst_n)
    begin
        en <= 2'b00;
    end
else
    if (!key_wr) 
        begin
            en <= 2'b01;
        end
    else
        if(!key_rd)
            begin
                en <= 2'b10;
            end

reg [3:0] cnt;
reg [7:0] memory;
reg [1:0] temp;

always @(posedge clk_sys or negedge rst_n)
if(!rst_n)
    begin
        cnt <= 'd0;
        temp <= 2'b00;
        sda_buffer <= 1'b1;
        flag <= 1'b1;
        data_out <= 8'd0;
        state <= 'd0;
    end
else
    case(state)
        0:begin
            if(scl)
                begin
                    if(en !=temp)
                        begin
                            sda_buffer <= 1'b0;
                            temp <= en;
                            memory <= 8'b1010_0000;
                            state <= 'd1;
                        end
                    else
                        state <= 'd0;
                end
            else
                begin
                    state <= 'd0;
                end
        end  
        1:begin
            if(scl == 1'b0 && (cnt < 'd8))
                begin
                    sda_buffer <= memory[7];
                    cnt <= cnt + 1'b1;
                    memory <= {memory[6:0],memory[7]};
                    state <= 'd1;
                end
            else
                begin
                    if(scl == 1'b0 && (cnt <='d8))
                        begin
                            cnt <= 'd0;
                            flag <= 1'b0;
                            state <= 'd2;
                        end
                    else
                        begin
                            state <= 'd1;//此时等待scl为0时
                        end
                end
        end
        2:begin
            //if(!sda)
                begin
                    state <= 'd3;
                    memory <= 8'd0;//高字节地址
                end
           /* else
                begin
                    state <= 'd0;
                end */
        end
        3:begin
            if(scl == 1'b0 && (cnt < 'd8))
                begin
                    flag <= 1'b1;
                    sda_buffer <= memory[7];
                    cnt <= cnt + 1'b1;
                    memory <= {memory[6:0],memory[7]};
                    state <= 'd3;
                end
            else
                if(scl == 1'b0 && (cnt == 'd8) )
                    begin
                        cnt <= 'd0;
                        flag <= 1'b0;
                        state <= 'd4;
                    end
                else
                    begin
                        state <= 'd3;
                    end           
        end
        4:begin
          //  if(!sda)
                begin
                    memory <= 8'h00;
                    state <= 'd5; 
                end
            //  else
            //      begin
            //          state <= 'd0;
            //      end 
        end
        5:begin
            if(scl == 1'b0 && (cnt < 'd8))
                begin
                    flag <= 1'b1;
                    sda_buffer <= memory[7];
                    cnt <= cnt + 1'b1;
                    memory <= {memory[6:0],memory[7]};
                    state <= 'd5;
                end
            else
                if(scl == 1'b0 && (cnt == 'd8) )
                    begin
                        cnt <= 'd0;
                        flag <= 1'b0;
                        state <= 'd6;
                    end
                else
                    begin
                        state <= 'd5;
                    end           
        end
        6:begin
            //if(!sda)
                begin
                    if(temp == 2'b01)
                        begin
                            state <= 'd7;
                            memory <= data_in[7:0];
                        end
                    if(temp == 2'b10)
                        begin
                            state <= 'd11;
                        end 
                end
            //else
            //    begin
            //        state <= 'd0;
            //    end
        end
        7:begin
            if(scl == 1'b0 && (cnt < 'd8))
                begin
                    flag <= 1'b1;
                    sda_buffer <= memory[7];
                    cnt <= cnt + 1'b1;
                    memory <= {memory[6:0],memory[7]};
                    state <= 'd7;
                end
            else
                if(scl == 1'b0 && (cnt == 'd8) )
                    begin
                        cnt <= 'd0;
                        flag <= 1'b0;
                        state <= 'd8;
                    end
                else
                    begin
                        state <= 'd7;
                    end           
        end
        8:begin
           // if(!sda)
                begin
                    state <= 'd9;
                end
            //else
            //    begin
            //        state <= 'd0;
            //    end 
        end
        9:begin
            if(scl == 1'b0)
                begin
                    flag <= 1'b1;
                    sda_buffer <= 1'b0;
                    state <= 'd10;
                end
            else
                begin
                    state <= 'd9;
                end
        end
        10:begin
            if(scl)
                begin
                    sda_buffer <= 1'b1;
                    state <= 'd0;
                end
            else
                begin
                    state <= 'd9;
                end 
        end//写的结束
        //_____________________________________________________________________________________________

        11:begin
            flag <= 1'b1;
            sda_buffer <= 1'b1;
            state <= 'd12;
        end
        12:begin
            sda_buffer <= 1'b0;
            state <= 'd13;
            memory <= 8'b1010_0001;
        end
        13:begin
            if(scl == 1'b0 && (cnt < 'd8))
                begin
                    flag <= 1'b1;
                    sda_buffer <= memory[7];
                    cnt <= cnt + 1'b1;
                    memory <= {memory[6:0],memory[7]};
                    state <= 'd13;
                end
            else
                if(scl == 1'b0 && (cnt == 'd8) )
                    begin
                        cnt <= 'd0;
                        flag <= 1'b0;
                        state <= 'd14;
                    end
                else
                    begin
                        state <= 'd13;
                    end           
        end
        14:begin
            //if(!sda)
                begin
                    state <= 'd15;
                end
            //else
            //    begin
            //        state <= 'd0;
            //    end 
        end
        15:begin
            if(scl == 1'b1 && (cnt <= 'd8))
                begin
                    cnt <= cnt + 1'b1;
                    memory <= {memory[6:0],sda};
                    state <= 'd15;
                end
            else
                if(scl == 1'b0 && (cnt == 'd8))
                    begin
                        cnt <='d0;
                        flag <= 1'b1;
                        state <= 'd16;
                        sda_buffer <= 1'b1;
                    end
                else
                    begin
                        state <= 'd15;
                    end 
        end
        16:begin
                data_out <= memory;
                state <= 'd17;
        end
        17:begin
            if(scl == 1'b0)
                begin
                    sda_buffer <= 1'b0;
                    state <= 'd18;
                end
            else
                begin
                    state <= 'd17;
                end
        end
        18:begin
            if(scl == 'd1)
                begin
                    sda_buffer <= 1'b1;
                    state <= 'd0;
                end
            else
                begin
                    state <= 'd18;
                end 
        end 
        default  : state <='d0;
    endcase

endmodule

对于我的理解iic协议，就是一个通过一条信号线sda线，来传输数据。在scl的高电平的时候进行采集sda数据以及开始结束的跳变沿变化，在scl的低电平时，进行sda的写入数据。刚开始的，scl为高电平，进行采集对于程序的开始，然后发送控制字，进行对写操作。
今天的问题是：了解eeprom，与iic的控制设计。

对于今天python的学习。
input（）的使用。
可以赋值给变量。
input（）赋值给变量的类型都是字符串型。
所以进行条件判断只能是字符型。
除非是条件强制转换为整型.
int(input())